p.Reg = r1
		p.To.Type = obj.TYPE_REG
		p.To.Reg = r

	case ssa.OpPPC64ADDZE:
		p := s.Prog(v.Op.Asm())
		p.From.Type = obj.TYPE_REG
		p.From.Reg = v.Args[0].Reg()
		p.To.Type = obj.TYPE_REG
		p.To.Reg = v.Reg0()

	case ssa.OpPPC64ADDZEzero, ssa.OpPPC64SUBZEzero:
		p := s.Prog(v.Op.Asm())
		p.From.Type = obj.TYPE_REG
		p.From.Reg = ppc64.REG_R0
		p.To.Type = obj.TYPE_REG
		p.To.Reg = v.Reg()

		{name: "FMOVDfpgp", argLength: 1, reg: fpgp, asm: "FMOVD"}, // move float64 to int64 (no conversion)
		{name: "FMOVSgpfp", argLength: 1, reg: gpfp, asm: "FMOVS"}, // move 32bits from int to float reg (no conversion)
		{name: "FMOVSfpgp", argLength: 1, reg: fpgp, asm: "FMOVS"}, // move 32bits from float to int reg, zero extend (no conversion)

		// conversions

		my ($name, $type) = parseparam($p);
		my $reg = "";
		if($name eq "err" && !$plan9) {
			$reg = "e1";
			$ret[2] = $reg;
			$do_errno = 1;
		} elsif($name eq "err" && $plan9) {
			$ret[0] = "r0";
			$ret[2] = "e1";
			next;
		} else {
			$reg = sprintf("r%d", $i);
			$ret[$i] = $reg;
		}
		if($type eq "bool") {
			$reg = "$reg != 0";
		}
		if($type eq "int64" && $_32bit ne "") {

	}
	memmove(dst, src, size)

	// Move pointers returned in registers to a place where the GC can see them.
	for i := range regs.Ints {
		if regs.ReturnIsPtr.Get(i) {
			regs.Ptrs[i] = unsafe.Pointer(regs.Ints[i])
		}
	}
}

// typedslicecopy should be an internal detail,
// but widely used packages access it using linkname.

spec:
  phase: STATS
  targetRef:
    kind: {{ .TargetKind }}
    group: {{ .TargetGroup }}
    name: {{ .TargetName }}
  {{- if .TestWasmModuleURL }}
  url: {{ .TestWasmModuleURL }}
  {{- end }}
  imagePullSecret: reg-cred
  {{- if .ImagePullPolicy }}
  imagePullPolicy: {{ .ImagePullPolicy }}

	a.retPop = c.retPop

	// Convert from C to Go ABI.
	var regs abi.RegArgs
	var frame [callbackMaxFrame]byte
	goArgs := unsafe.Pointer(&frame)
	for _, part := range c.abiMap.parts {
		switch part.kind {
		case abiPartStack:
			memmove(add(goArgs, part.dstStackOffset), add(a.args, part.srcStackOffset), part.len)
		case abiPartReg:
			goReg := unsafe.Pointer(&regs.Ints[part.dstRegister])

	STMG	R6, R15, 48(R15)		// Save non-volatile regs.
	BL	runtime·load_g(SB)		// Saved by racecall.
	CMPBNE	R2, $0, rest			// raceGetProcCmd?
	MOVD	g_m(g), R2			// R2 = thread.
	MOVD	m_p(R2), R2			// R2 = processor.
	MVC	$8, p_raceprocctx(R2), (R3)	// *R3 = ThreadState *.
	LMG	48(R15), R6, R15		// Restore non-volatile regs.
	BR	R14				// Return to C.
rest:	MOVD	g_m(g), R4			// R4 = current thread.

	C_AND0CON
	C_ADDCON // -0x800 <= v < 0
	C_ANDCON // 0 < v <= 0xFFF
	C_LCON   // other 32
	C_DCON   // other 64 (could subdivide further)
	C_SACON  // $n(REG) where n <= int12
	C_SECON
	C_LACON // $n(REG) where int12 < n <= int32
	C_LECON
	C_DACON // $n(REG) where int32 < n
	C_STCON // $tlsvar
	C_SBRA
	C_LBRA
	C_SAUTO
	C_LAUTO
	C_SEXT
	C_LEXT
	C_ZOREG
	C_SOREG
	C_LOREG
	C_GOK

			continue
		}
		argRegs = intArgRegs
		unlock(&finlock)
		if raceenabled {
			racefingo()
		}
		for fb != nil {
			for i := fb.cnt; i > 0; i-- {
				f := &fb.fin[i-1]

				var regs abi.RegArgs
				// The args may be passed in registers or on stack. Even for
				// the register case, we still need the spill slots.
				// TODO: revisit if we remove spill slots.
				//

//		On ARM64:
//			offset = (reg&31)<<16 | shifttype<<22 | (count&63)<<10
//			shifttype = 0, 1, 2 for <<, >>, ->
//
//	(reg, reg)
//		A destination register pair. When used as the last argument of an instruction,
//		this form makes clear that both registers are destinations.
//		Encoding:
//			type = TYPE_REGREG
//			reg = first register
//			offset = second register
//
//	[reg, reg, reg-reg]