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Results 41 - 43 of 43 for ifeq (0.03 sec)
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src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(Eq16 x y) => (SEQZ (SUB <x.Type> (ZeroExt16to64 x) (ZeroExt16to64 y))) (Eq8 x y) => (SEQZ (SUB <x.Type> (ZeroExt8to64 x) (ZeroExt8to64 y))) (Eq(64|32)F ...) => (FEQ(D|S) ...) (NeqPtr x y) => (Not (EqPtr x y)) (Neq64 x y) => (Not (Eq64 x y)) (Neq32 x y) => (Not (Eq32 x y)) (Neq16 x y) => (Not (Eq16 x y)) (Neq8 x y) => (Not (Eq8 x y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
platforms/core-configuration/model-core/src/main/java/org/gradle/internal/instantiation/generator/AsmBackedClassGenerator.java
Label end = new Label(); Label notArray = new Label(); _ALOAD(2); _INSTANCEOF(OBJECT_ARRAY_TYPE); _IFEQ(notArray); // (Object[]) args _ALOAD(2); _CHECKCAST(OBJECT_ARRAY_TYPE); _GOTO(end); // new Object[] { args }
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Fri May 24 15:40:00 UTC 2024 - 100.6K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
if p.Scond&rmSuffixBit == 0 { ins.funct3 = uint32(RM_RTZ) } else { ins.funct3 = uint32(p.Scond &^ rmSuffixBit) } case AFNES, AFNED: // Replace FNE[SD] with FEQ[SD] and NOT. if p.To.Type != obj.TYPE_REG { p.Ctxt.Diag("%v needs an integer register output", p) return nil } if ins.as == AFNES { ins.as = AFEQS } else { ins.as = AFEQD
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0)