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Results 21 - 23 of 23 for ORR (0.02 sec)

  1. src/cmd/asm/internal/asm/parse.go

    	case lex.LSH:
    		op = 0
    	case lex.RSH:
    		op = 1
    	case lex.ARR:
    		op = 2
    	case lex.ROT:
    		// following instructions on ARM64 support rotate right
    		// AND, ANDS, TST, BIC, BICS, EON, EOR, ORR, MVN, ORN
    		op = 3
    	}
    	tok := p.next()
    	str := tok.String()
    	var count int16
    	switch tok.ScanToken {
    	case scanner.Ident:
    		if p.arch.Family == sys.ARM64 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Feb 21 14:34:57 UTC 2024
    - 36.9K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/arm/asm5.go

    		rt := int(p.To.Reg)
    		if r == 0 {
    			r = rt
    		}
    		x, y := immrot2a(uint32(c.instoffset))
    		var as2 obj.As
    		switch p.As {
    		case AADD, ASUB, AORR, AEOR, ABIC:
    			as2 = p.As // ADD, SUB, ORR, EOR, BIC
    		case ARSB:
    			as2 = AADD // RSB -> RSB/ADD pair
    		case AADC:
    			as2 = AADD // ADC -> ADC/ADD pair
    		case ASBC:
    			as2 = ASUB // SBC -> SBC/SUB pair
    		case ARSC:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 79.4K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/arm64/asm7.go

    			o1 |= 1 << 10
    		} else {
    			o1 |= 3 << 10
    		}
    		o1 |= ((uint32(v) & 0x1FF) << 12) | (uint32(p.To.Reg&31) << 5) | uint32(p.From.Reg&31)
    
    	case 24: /* mov/mvn Rs,Rd -> add $0,Rs,Rd or orr Rs,ZR,Rd */
    		rf := int(p.From.Reg)
    		rt := int(p.To.Reg)
    		if rf == REGSP || rt == REGSP {
    			if p.As == AMVN || p.As == AMVNW {
    				c.ctxt.Diag("illegal SP reference\n%v", p)
    			}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
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