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Results 11 - 20 of 24 for DIVD (0.13 sec)

  1. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    
    		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},                // arg0 & arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  2. src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go

    	{VNMLS_EQ_F32, []int{2, 1, 0}, "VNMLS", "NMULSF"},
    	{VNMLS_EQ_F64, []int{2, 1, 0}, "VNMLS", "NMULSD"},
    	{VDIV_EQ_F32, []int{2, 1, 0}, "VDIV", "DIVF"},
    	{VDIV_EQ_F64, []int{2, 1, 0}, "VDIV", "DIVD"},
    	{VNEG_EQ_F32, []int{1, 0}, "VNEG", "NEGF"},
    	{VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"},
    	{VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"},
    	{VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 11.9K bytes
    - Viewed (0)
  3. src/runtime/sys_linux_s390x.s

    	MOVD	$r+8(FP), R2
    	MOVW	flags+0(FP), R3
    	MOVW	$SYS_pipe2, R1
    	SYSCALL
    	MOVW	R2, errno+16(FP)
    	RET
    
    TEXT runtimeĀ·usleep(SB),NOSPLIT,$16-4
    	MOVW	usec+0(FP), R2
    	MOVD	R2, R4
    	MOVW	$1000000, R3
    	DIVD	R3, R2
    	MOVD	R2, 8(R15)
    	MOVW	$1000, R3
    	MULLD	R2, R3
    	SUB	R3, R4
    	MOVD	R4, 16(R15)
    
    	// nanosleep(&ts, 0)
    	ADD	$8, R15, R2
    	MOVW	$0, R3
    	MOVW	$SYS_nanosleep, R1
    	SYSCALL
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 24 18:53:44 UTC 2023
    - 12.5K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/ppc64.s

    	MULLWVCC R3, R4, R5             // 7ca41dd7
    	MULHWUCC R3, R4, R5             // 7ca41817
    	MULLDV R3, R4, R5               // 7ca41dd2
    	MULLDVCC R3, R4, R5             // 7ca41dd3
    
    	DIVD R3,R4                      // 7c841bd2
    	DIVD R3, R4, R5                 // 7ca41bd2
    	DIVW R3, R4                     // 7c841bd6
    	DIVW R3, R4, R5                 // 7ca41bd6
    	DIVDCC R3,R4, R5                // 7ca41bd3
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/ARMOps.go

    		{name: "NMULD", argLength: 2, reg: fp21, asm: "NMULD", commutative: true}, // -(arg0 * arg1)
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                      // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                      // arg0 / arg1
    
    		{name: "MULAF", argLength: 3, reg: fp31, asm: "MULAF", resultInArg0: true}, // arg0 + (arg1 * arg2)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 41K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV"},   // arg0/arg1
    		{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0/arg1
    
    		{name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},   // arg0/arg1 (signed 64-bit)
    		{name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},   // arg0/arg1 (signed 32-bit)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/S390XOps.go

    		{name: "MULHDU", argLength: 2, reg: gp21tmp, asm: "MULHDU", typ: "Int64", commutative: true, resultInArg0: true, clobberFlags: true}, // (arg0 * arg1) >> width
    
    		{name: "DIVD", argLength: 2, reg: gp21tmp, asm: "DIVD", resultInArg0: true, clobberFlags: true},   // arg0 / arg1
    		{name: "DIVW", argLength: 2, reg: gp21tmp, asm: "DIVW", resultInArg0: true, clobberFlags: true},   // arg0 / arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 52.5K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/prove.go

    			if b.Func.Config.arch != "386" && b.Func.Config.arch != "amd64" {
    				break
    			}
    			divr := v.Args[1]
    			divrLim, divrLimok := ft.limits[divr.ID]
    			divd := v.Args[0]
    			divdLim, divdLimok := ft.limits[divd.ID]
    			if (divrLimok && (divrLim.max < -1 || divrLim.min > -1)) ||
    				(divdLimok && divdLim.min > mostNegativeDividend[v.Op]) {
    				// See DivisionNeedsFixUp in rewrite.go.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:30:21 UTC 2024
    - 48.9K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Mod8 x y) => (Mod32 (SignExt8to32 x) (SignExt8to32 y))
    (Mod8u x y) => (Mod32u (ZeroExt8to32 x) (ZeroExt8to32 y))
    (Mod64 x y) && buildcfg.GOPPC64 >=9 => (MODSD x y)
    (Mod64 x y) && buildcfg.GOPPC64 <=8 => (SUB x (MULLD y (DIVD x y)))
    (Mod64u x y) && buildcfg.GOPPC64 >= 9 => (MODUD x y)
    (Mod64u x y) && buildcfg.GOPPC64 <= 8 => (SUB x (MULLD y (DIVDU x y)))
    (Mod32 x y) && buildcfg.GOPPC64 >= 9 => (MODSW x y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  10. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	CNTLZD:         "cntlzd",
    	CNTLZDCC:       "cntlzd.",
    	DCBF:           "dcbf",
    	DCBST:          "dcbst",
    	DCBT:           "dcbt",
    	DCBTST:         "dcbtst",
    	DIVD:           "divd",
    	DIVDCC:         "divd.",
    	DIVDO:          "divdo",
    	DIVDOCC:        "divdo.",
    	DIVDU:          "divdu",
    	DIVDUCC:        "divdu.",
    	DIVDUO:         "divduo",
    	DIVDUOCC:       "divduo.",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
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