(Neg(64|32|16|8) ...) => (NEG ...)
(Neg(64|32)F ...) => (FNEG ...)

(Com(64|32|16|8) x) => (NOR x x)

// Lowering boolean ops
(AndB ...) => (AND ...)
(OrB ...) => (OR ...)
(Not x) => (XORconst [1] x)

// Merge logical operations
(AND x (NOR y y)) => (ANDN x y)
(OR x (NOR y y)) => (ORN x y)

// Lowering comparisons
(EqB x y)  => (ANDconst [1] (EQV x y))

  }
  pass_manager.clear();
  pass_manager.addPass(mlir::odml::createLegalizeStablehloToVhloPass());
  if (failed(pass_manager.run(module))) {
    return status_handler.Combine(
        absl::InvalidArgumentError("VHLO lowering failed"));
  }

  // Write MLIR Stablehlo dialect into FlatBuffer
  OpOrArgLocNameMapper op_or_arg_name_mapper;
  tflite::FlatbufferExportOptions options;
  options.toco_flags = toco_flags;

  mlir::OpPassManager& func_pm = pm_.nest<mlir::func::FuncOp>();

  // Prepare the imported graph.
  func_pm.addPass(mlir::CreateExecutorDialectToFunctionalConversionPass());

  // Run TFR lowering, inlining and raising to tf.
  func_pm.addPass(mlir::TFR::CreateDecomposeTFOpsPass(tfr_module_));
  func_pm.addPass(mlir::TFR::CreateRaiseToTFOpsPass(
      tfr_module_, /*materialize_derived_attrs=*/true));

//
// Especially early in transformation, it is common to have dcasts on
// all operands to ops that must operate with the expressed type (typically
// math ops prior to lowering to target-specific, quantized kernels).
def Quantization_DequantizeCastOp : Quantization_Op<"dcast", [Pure]> {
  let arguments = (ins quant_RealValueType:$arg);
  let results = (outs quant_RealValueType);
}

    // CHECK: tf.Atan2
    // expected-remark@+1 {{lowering requires bounded tensor operands}}
    %0 = "tf.Atan2"(%arg0, %arg0) : (tensor<*xf32>, tensor<*xf32>) -> tensor<*xf32>

    func.return %0 : tensor<*xf32>
  }

  // CHECK-LABEL: dynamic_operand
  func.func @dynamic_operand(%arg0: tensor<?xf32>) -> tensor<?xf32> {
    // CHECK: tf.Atan2
    // expected-remark@+1 {{lowering requires bounded tensor operands}}

	{name: "Arg", aux: "SymOff", symEffect: "Read", zeroWidth: true}, // argument to the function.  aux=GCNode of arg, off = offset in that arg.

	// Like Arg, these are generic ops that survive lowering. AuxInt is a register index, and the actual output register for each index is defined by the architecture.
	// AuxInt = integer argument index (not a register number). ABI-specified spill loc obtained from function

    pm.addPass(
        mlir::odml::createPrintOpStatsPass(GetAcceptedStableHLODialects()));
  }

  if (failed(pm.run(tf_module))) {
    return tensorflow::errors::Aborted("Lowering to StableHLO failed.");
  }

  return absl::OkStatus();
}

tensorflow::Status RunConverter(const PassPipelineCLParser& pass_pipeline) {
  DialectRegistry registry;
  registerAllDialects(registry);

// faultOnLoad is true if a load to an address below minZeroPage will trigger a SIGSEGV.
var faultOnLoad = buildcfg.GOOS != "aix"

// nilcheckelim2 eliminates unnecessary nil checks.
// Runs after lowering and scheduling.
func nilcheckelim2(f *Func) {
	unnecessary := f.newSparseMap(f.NumValues()) // map from pointer that will be dereferenced to index of dereferencing value in b.Values[]
	defer f.retSparseMap(unnecessary)

  let description = [{
    The TensorFlow Device dialect.

    This dialect contains operations to describe/launch computations on devices.
    These operations do not map 1-1 to TensorFlow ops and requires a lowering
    pass later to transform them into Compile/Run op pairs, like XlaCompile and
    XlaRun.
}];

  let cppNamespace = "::mlir::tf_device";
}

        // Wrap these special attributes as a special TFR constant, so the SSA
        // value has a valid type to be used as TFR function argument. These
        // attributes are not expected to be manipulated by the lowering passes.
        if (mlir::isa<TypeAttr>(attribute) || mlir::isa<ArrayAttr>(attribute) ||
            mlir::isa<StringAttr>(attribute) ||
            mlir::isa<FlatSymbolRefAttr>(attribute)) {