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Results 31 - 40 of 45 for use_cudnn_on_gpu (0.39 sec)

  1. tensorflow/compiler/mlir/lite/tests/prepare-tf.mlir

      %0 = "tf.Conv2D"(%arg0, %arg1) {data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 1, 1], use_cudnn_on_gpu = true} : (tensor<?x?x?x96xf32>, tensor<3x3x96x?xf32>) -> tensor<?x?x?x?xf32>
      func.return %0 : tensor<?x?x?x?xf32>
    // CHECK: tf.Conv2D
    }
    
    // CHECK-LABEL: conv2d_f16
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed May 29 07:26:59 UTC 2024
    - 59.8K bytes
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  2. tensorflow/compiler/mlir/tensorflow/tests/tf_optimize.mlir

      // CHECK: %[[CONV:.*]] = "tf.Conv2D"(%arg0, %[[CST]]) <{data_format = "NHWC", dilations = [1, 2, 3, 1], explicit_paddings = [], padding = "SAME", strides = [1, 4, 5, 1], use_cudnn_on_gpu = true}>
      // CHECK: return %[[CONV]] : tensor<1x28x23x2xf32>
    }
    
    // CHECK-LABEL: @notfuseMulIntoConv2d
    // filter and multiply are not broadcastable
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9.5K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/stablehlo/tests/legalize_hlo.mlir

    // CHECK:           %[[VAL_10:.*]] = "tf.Conv2D"(%[[VAL_5]], %[[VAL_9]]) <{data_format = "NHWC", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "VALID", strides = [1, 1, 1, 1], use_cudnn_on_gpu = true}> : (tensor<16x32x1x256xbf16>, tensor<1x1x256x256xbf16>) -> tensor<16x32x1x256xbf16>
    // CHECK:           %[[VAL_11:.*]] = "tf.Const"() <{value = dense<[0, 1, 3, 2]> : tensor<4xi64>}> : () -> tensor<4xi64>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed May 29 07:26:59 UTC 2024
    - 340.2K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/quantization/tensorflow/tests/insert_custom_aggregation_ops.mlir

        %0 = "tf.Conv2D"(%arg0, %arg1) {attr_map = "0:strides,1:use_cudnn_on_gpu,2:padding,3:explicit_paddings,4:dilations", data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "VALID", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true} : (tensor<*xf32>, tensor<*xf32>) -> tensor<*xf32>
        %1 = "tf.Relu6"(%0) : (tensor<*xf32>) -> tensor<*xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri May 10 04:07:09 UTC 2024
    - 32.1K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/lite/tests/debuginfo/v1_1.0_224_frozen.wrong_attr.line.part.pbtxt

        }
      }
      attr {
        key: "strides"
        value {
          list {
            i: 1
            i: 2
            i: 2
            i: 1
          }
        }
      }
      attr {
        key: "use_cudnn_on_gpu"
        value {
          b: true
        }
      }
    }
    node {
      name: "MobilenetV1/Conv2d_0/BatchNorm/gamma"
      op: "Const"
      attr {
        key: "dtype"
        value {
          type: DT_FLOAT
        }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jul 27 18:59:05 UTC 2023
    - 16.2K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/lite/tests/debuginfo/v1_1.0_224_frozen.wrong_attr.stack.part.pbtxt

        }
      }
      attr {
        key: "strides"
        value {
          list {
            i: 1
            i: 2
            i: 2
            i: 1
          }
        }
      }
      attr {
        key: "use_cudnn_on_gpu"
        value {
          b: true
        }
      }
    }
    node {
      name: "MobilenetV1/Conv2d_0/BatchNorm/gamma"
      op: "Const"
      attr {
        key: "dtype"
        value {
          type: DT_FLOAT
        }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jul 27 18:59:05 UTC 2023
    - 16.4K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf-prefer-tf2xla.mlir

    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Apr 06 15:32:52 UTC 2024
    - 15.8K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/quantization/tensorflow/tests/replace_cast_hacks_with_tf_xla_ops.mlir

        %3 = "tf.Sub"(%2, %arg6) : (tensor<2x3x3x2xi32>, tensor<i32>) -> tensor<2x3x3x2xi32>
        %4 = "tf.Conv2D"(%1, %3) {dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true} : (tensor<1x3x4x3xi32>, tensor<2x3x3x2xi32>) -> tensor<1x3x2x2xi32>
        %5 = "tf.AddV2"(%4, %arg2) : (tensor<1x3x2x2xi32>, tensor<2xi32>) -> tensor<1x3x2x2xi32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 81K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/lite/tests/dilated-conv.mlir

      %7 = "tf.Conv2D"(%6, %4) {data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "VALID", strides = [1, 1, 1, 1], use_cudnn_on_gpu = true} : (tensor<4x960x1x64xf32>, tensor<3x1x64x128xf32>) -> tensor<4x958x1x128xf32>
      %8 = "tf.Squeeze"(%7) {device = "", squeeze_dims = [2]} : (tensor<4x958x1x128xf32>) -> tensor<4x958x128xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 44.7K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/lite/transforms/legalize_patterns.td

                                 (TFL_MatrixDiagOp $diagonal)>;
    
    def LegalizeConv2DBackpropInput : Pat<
      (TF_Conv2DBackpropInputOp $input_sizes, $filter, $out_backprop,
         IsIntList1XY1:$strides,
         BoolAttr:$use_cudnn_on_gpu,
         IsSameOrValid:$padding,
         I64ArrayAttr:$explicit_paddings,
         IsDataFormatNHWC:$data_format,
         IsAllOnes:$dilations),
      (TFL_TransposeConvOp $input_sizes,
         (TFL_TransposeOp $filter,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 04 13:30:42 UTC 2024
    - 28.5K bytes
    - Viewed (0)
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