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Results 31 - 40 of 200 for if64 (0.1 sec)

  1. test/codegen/bits.go

    func bitRotateAndMask(io64 [8]uint64, io32 [4]uint32, io16 [4]uint16, io8 [4]uint8) {
    	// ppc64x: "RLDICR\t[$]0, R[0-9]*, [$]47, R"
    	io64[0] = io64[0] & 0xFFFFFFFFFFFF0000
    	// ppc64x: "RLDICL\t[$]0, R[0-9]*, [$]16, R"
    	io64[1] = io64[1] & 0x0000FFFFFFFFFFFF
    	// ppc64x: -"SRD", -"AND", "RLDICL\t[$]60, R[0-9]*, [$]16, R"
    	io64[2] = (io64[2] >> 4) & 0x0000FFFFFFFFFFFF
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 7.8K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/tensorflow/tests/legalize_tfg.mlir

        %VarHandleOp, %ctl = VarHandleOp device("/CPU:0") name("x") {_output_shapes = [#tf_type.shape<>], allowed_devices = [], container = "a", dtype = i64, shape = #tf_type.shape<>, shared_name = "x"} : () -> (tensor<!tf_type.resource<tensor<i64>>>)
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 2.9K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/lite/stablehlo/tests/uniform-quantized-stablehlo-to-tfl.mlir

    func.func @dynamic_slice(
        %arg0: tensor<4x4x!quant.uniform<i8:f32, 3.000000e-01:-5>>,
        %arg1: tensor<i64>,
        %arg2: tensor<i64>
      ) -> tensor<2x1x!quant.uniform<i8:f32, 3.000000e-01:-5>> {
      %0 = "stablehlo.dynamic_slice"(%arg0, %arg1, %arg2) {
        slice_sizes = array<i64: 2, 1>
      } : (
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue May 14 17:10:32 UTC 2024
    - 106.2K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/quantization/stablehlo/passes/bridge/legalize_tf_quant_test.cc

            quantization_axis = -1 : i64, quantization_min_val = -128 : i64, quantization_max_val = 127 : i64
          } : (tensor<1xf32>, tensor<f32>, tensor<i32>) -> tensor<1x!tf_type.qint8>
          %1 = "tf.UniformDequantize"(%0, %scales, %zps) {
            quantization_axis = -1 : i64, quantization_min_val = -128 : i64, quantization_max_val = 127 : i64
          } : (tensor<1x!tf_type.qint8>, tensor<f32>, tensor<i32>) -> tensor<1xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Feb 29 18:43:55 UTC 2024
    - 7.2K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/tensorflow/tests/constant_op_device_assignment.mlir

      // CHECK-NEXT: %[[RESULT_0:.*]] = "tf.Const"() <{value = dense<1> : tensor<i64>}> : () -> tensor<i64>
      // CHECK-NEXT: %[[RESULT_1:.*]] = "tf.AddV2"(%[[RESULT_0]], %[[RESULT_0]]) : (tensor<i64>, tensor<i64>) -> tensor<i64>
      %0 = "tf.Const"() {value = dense<1> : tensor<i64>} : () -> tensor<i64>
      %1 = "tf.AddV2"(%0, %0) : (tensor<i64>, tensor<i64>) -> tensor<i64>
      func.return
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 1.5K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/quantization/tensorflow/tests/lift_hashtable_ops_as_args.mlir

        %4 = "tf.AddV2"(%2, %3) {device = ""} : (tensor<i64>, tensor<i64>) -> tensor<i64>
        %5 = "tf.LookupTableFindV2"(%0, %arg0, %cst) {device = ""} : (tensor<!tf_type.resource>, tensor<?x!tf_type.string>, tensor<i64>) -> tensor<*xi64>
        %6 = "tf.AddV2"(%5, %4) {device = ""} : (tensor<*xi64>, tensor<i64>) -> tensor<*xi64>
        return %6 : tensor<*xi64>
      }
    // Check that HashTable op is lifted.
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Mar 15 05:41:44 UTC 2024
    - 13.5K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/quantization/stablehlo/tests/pipelines/process_nchw_tensor.mlir

    // CHECK: %[[ADD:.+]] = stablehlo.add %[[CONV]], %[[BIAS_CONST]] : tensor<1x5x5x4xf32>
    // CHECK: %[[REDUCE_WINDOW_MAX:.+]] = "stablehlo.reduce_window"(%[[ADD]], %[[INIT_VALUE_CONST:.+]])
    // CHECK: <{window_dimensions = array<i64: 1, 2, 2, 1>, window_strides = array<i64: 1, 2, 2, 1>}>
    // CHECK: stablehlo.maximum
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Apr 18 20:32:46 UTC 2024
    - 12.6K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tensorflow/tests/embedding_pipelining.mlir

        "tf.AssignAddVariableOp"(%37, %cst_12) {_has_manual_control_dependencies = true, _replication_info = "while/cluster_while_body_451", _xla_compile_device_type = "TPU", device = ""} : (tensor<*x!tf_type.resource<tensor<i64>>>, tensor<i64>) -> ()
    
        return %res_n, %arg1 : tensor<i32>, tensor<*x!tf_type.resource<tensor<i64>>>
      }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 33.1K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/tfrt/tests/tf_to_corert/batch_function_deduplicate.mlir

    {_xla_inferred_shapes = [#tf_type.shape<*>, #tf_type.shape<*>], allowed_batch_sizes = [64, 128, 256], batch_timeout_micros = 5000 : i64, batching_queue = "", container = "", device = "/job:localhost/replica:0/task:0/device:CPU:0", enable_large_batch_splitting = true, f = @compute_0, max_batch_size = 256 : i64, max_enqueued_batches = 10000 : i64, num_batch_threads = 2 : i64, operandSegmentSizes = array<i32: 1, 1>, shared_name = "computation"} : (tensor<?x?xi32>, tensor<?x?xi32>) -> (tensor<*xi32>, tensor<*xi32>)...
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Aug 14 15:35:49 UTC 2023
    - 3.5K bytes
    - Viewed (0)
  10. src/archive/tar/reader.go

    			continue // Keep the original USTAR value
    		}
    		var id64 int64
    		switch k {
    		case paxPath:
    			hdr.Name = v
    		case paxLinkpath:
    			hdr.Linkname = v
    		case paxUname:
    			hdr.Uname = v
    		case paxGname:
    			hdr.Gname = v
    		case paxUid:
    			id64, err = strconv.ParseInt(v, 10, 64)
    			hdr.Uid = int(id64) // Integer overflow possible
    		case paxGid:
    			id64, err = strconv.ParseInt(v, 10, 64)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 08 01:59:14 UTC 2024
    - 26.8K bytes
    - Viewed (0)
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