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Results 11 - 20 of 123 for art4 (0.04 sec)

  1. tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_weights.mlir

    // CHECK: %[[MATMUL_1:.*]] = "tf.MatMul"(%arg3, %arg4) <{transpose_a = false, transpose_b = false}> {device = ""} : (tensor<1x1024xf32>, tensor<1024x1024xf32>) -> tensor<1x1024xf32>
    // CHECK: %[[IDENTITY:.*]] = "tf.Identity"(%arg4) {device = ""} : (tensor<1024x1024xf32>) -> tensor<1024x1024xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 42K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/lite/tests/flatbuffer2mlir/basic_lstm.mlir

    // Ensure basic_lstm roundtrip exactly
    
    func.func @main(%arg0: tensor<1x384xf32>, %arg1: tensor<1x96xf32>, %arg2: tensor<384x480xf32>, %arg3: tensor<384xf32>, %arg4: tensor<1x96xf32>) -> tensor<1x96xf32> {
    // CHECK-LABEL: @main
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 1.1K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nhwc.mlir

      %9 = "tf.Conv2D"(%8, %arg4)
           {
             data_format = "NCHW",
             dilations = [1, 1, 1, 1],
             explicit_paddings = [],
             padding = "VALID",
             strides = [1, 1, 1, 1]
           } : (tensor<?x64x56x56xf32>, tensor<1x1x64x256xf32>) -> tensor<?x256x56x56xf32>
    
      // CHECK: %[[CONV1:[0-9]*]] = "tf.Conv2D"(%[[MAX_POOL]], %arg4)
      // CHECK-SAME: data_format = "NHWC"
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 7.3K bytes
    - Viewed (0)
  4. tensorflow/compiler/mlir/tensorflow/tests/tpu_space_to_depth_pass.mlir

        %2 = "tf.Less"(%arg3, %0) {device = ""} : (tensor<i32>, tensor<i32>) -> tensor<i1>
        %3 = "tf.Greater"(%arg2, %arg4) {device = ""} : (tensor<i32>, tensor<i32>) -> tensor<i1>
        %4 = "tf.LogicalAnd"(%2, %3) {device = ""} : (tensor<i1>, tensor<i1>) -> tensor<i1>
        %5 = "tf.Less"(%arg2, %arg4) {device = ""} : (tensor<i32>, tensor<i32>) -> tensor<i1>
        %6 = "tf.LogicalAnd"(%1, %5) {device = ""} : (tensor<i1>, tensor<i1>) -> tensor<i1>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 37.4K bytes
    - Viewed (0)
  5. maven-core/src/main/java/org/apache/maven/project/DefaultProjectDependenciesResolver.java

                        // enable re-resolution
                        org.eclipse.aether.artifact.Artifact art = dep.getArtifact();
                        art = art.setFile(null).setVersion(art.getBaseVersion());
                        dep = dep.setArtifact(art);
                    }
                    collect.addDependency(dep);
                }
            }
    
    Registered: Wed Jun 12 09:55:16 UTC 2024
    - Last Modified: Wed Jun 12 07:49:10 UTC 2024
    - 9.3K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tfrt/tests/tf_to_corert/tf_to_corert_pipeline.mlir

    // CHECK-SAME: ([[in_chain:%.*]]: !tfrt.chain
    // CHECK-SAME: [[arg1:%.*]]: !tfrt_fallback.tf_tensor {tf._user_specified_name = "inputs"},
    // CHECK-SAME: [[arg2:%.*]]: !tfrt_fallback.tf_tensor, [[arg3:%.*]]: !tfrt_fallback.tf_tensor, [[arg4:%.*]]: !tfrt_fallback.tf_tensor, [[arg5:%.*]]: !tfrt_fallback.tf_tensor)
    // CHECK-SAME: -> (!tfrt.chain
    // CHECK: [[o1:%.*]] = tfrt_fallback_async.const_dense_tensor
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed May 08 00:18:59 UTC 2024
    - 7.7K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/lite/tests/shape-inference.mlir

    // CHECK-LABEL: testUnidirectionalSequenceLstmShapeInference
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 11.5K bytes
    - Viewed (0)
  8. tensorflow/compiler/mlir/tensorflow/tests/tpu-merge-variables-with-execute.mlir

      // CHECK-NEXT: %[[READ_3:.*]] = "tf.ReadVariableOp"(%[[ARG_4]])
      %read3 = "tf.ReadVariableOp"(%arg4) : (tensor<*x!tf_type.resource<tensor<8xf32>>>) -> tensor<8xf32>
      // CHECK-NEXT: "tf.AssignVariableOp"(%[[ARG_4]], %[[EXE]]#1)
      "tf.AssignVariableOp"(%arg4, %execute#2) : (tensor<*x!tf_type.resource<tensor<8xf32>>>, tensor<8xf32>) -> ()
      // CHECK-NEXT: return %[[READ_3]]
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Oct 31 08:59:10 UTC 2023
    - 24.5K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/lite/tests/legalize-tf-while.mlir

      func.return %0#2, %0#3, %0#4 : tensor<i32>, tensor<256x256xf32>, tensor<?x256x256xf32>
    }
    
    func.func @while_body_11_frozen0(%arg0: tensor<*xi32>, %arg1: tensor<*xi32>, %arg2: tensor<*xi32>, %arg3: tensor<*xf32>, %arg4: tensor<*xf32>) -> (tensor<*xi32>, tensor<*xi32>, tensor<*xi32>, tensor<*xf32>, tensor<*xf32>) {
      %cst = arith.constant dense<[1, 0]> : tensor<2xi32>
      %cst_0 = arith.constant dense<0> : tensor<i32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 5K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf-with-tf2xla-hlo-importer.mlir

        // CHECK: "mhlo.batch_norm_inference"({{.*}}, %arg1, %arg2, %arg3, %arg4) <{epsilon = 1.000000e-03 : f32, feature_index = 3 : i64}> : (tensor<8x8x8x8xf32>, tensor<8xf32>, tensor<8xf32>, tensor<8xf32>, tensor<8xf32>) -> tensor<8x8x8x8xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Apr 06 15:32:52 UTC 2024
    - 38.6K bytes
    - Viewed (0)
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