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src/cmd/compile/internal/ssa/op.go
// Inputs which do not need registers are not listed. inputs []inputInfo // clobbers encodes the set of registers that are overwritten by // the instruction (other than the output registers). clobbers regMask // outputs is the same as inputs, but for the outputs of the instruction. outputs []outputInfo } func (r *regInfo) String() string { s := "" s += "INS:\n" for _, i := range r.inputs {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 22 15:29:10 UTC 2024 - 18.7K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
} // must check literal pool here in case p generates many instructions if c.blitrl != nil { // Emit the constant pool just before p if p // would push us over the immediate size limit. if c.checkpool(op, pc+int32(m)) { // Back up to the instruction just // before the pool and continue with // the first instruction of the pool. p = op continue } }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/obj7.go
p.From.Class = 0 p.To.Class = 0 // Previously we rewrote $0 to ZR, but we have now removed this change. // In order to be compatible with some previous legal instruction formats, // reserve the previous conversion for some specific instructions. if p.From.Type == obj.TYPE_CONST && p.From.Offset == 0 && zrReplace[p.As] { p.From.Type = obj.TYPE_REG p.From.Reg = REGZERO }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 08 05:46:32 UTC 2023 - 28.4K bytes - Viewed (0) -
src/runtime/export_debug_test.go
println("trap in unknown function", funcname(f)) return false } if !sigctxtAtTrapInstruction(ctxt) { println("trap at non-INT3 instruction pc =", hex(ctxt.sigpc())) return false } switch status := sigctxtStatus(ctxt); status { case 0: // Frame is ready. Copy the arguments to the frame and to registers. // Call the debug function.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:41:45 UTC 2024 - 5.1K bytes - Viewed (0) -
src/cmd/link/internal/x86/asm.go
return } case ld.BuildModePIE, ld.BuildModeCShared, ld.BuildModePlugin: // We need get_pc_thunk. default: return } } // Generate little thunks that load the PC of the next instruction into a register. thunks := make([]loader.Sym, 0, 7+len(ctxt.Textp)) for _, r := range [...]struct { name string num uint8 }{ {"ax", 0}, {"cx", 1}, {"dx", 2}, {"bx", 3}, // sp
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 23 05:58:20 UTC 2023 - 13.6K bytes - Viewed (0) -
src/cmd/vendor/rsc.io/markdown/html.go
} } } } return false } func parseHTMLTag(p *parseState, s string, i int) (Inline, int, bool) { // “An HTML tag consists of an open tag, a closing tag, an HTML comment, // a processing instruction, a declaration, or a CDATA section.” if i+3 <= len(s) && s[i] == '<' { switch s[i+1] { default: return parseHTMLOpenTag(p, s, i) case '/': return parseHTMLClosingTag(p, s, i) case '!':
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jan 24 13:01:26 UTC 2024 - 11.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/genericOps.go
{name: "Cvt64Uto64F", argLength: 1}, // uint64 -> float64, only used on archs that has the instruction {name: "Cvt32Fto64U", argLength: 1}, // float32 -> uint64, only used on archs that has the instruction {name: "Cvt64Fto64U", argLength: 1}, // float64 -> uint64, only used on archs that has the instruction // pseudo-ops for breaking Tuple
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 42.6K bytes - Viewed (0) -
api/maven-api-core/src/main/java/org/apache/maven/api/Type.java
* * <p>It is nevertheless common to specify two or more types of path. For example, * a Java library may be compatible with either the class-path or the module-path, * and the user may have provided no instruction about which type to use. In such * case, the plugin may apply rules for choosing a path. See for example * {@link JavaPathType#CLASSES} and {@link JavaPathType#MODULES}.</p> */ @Nonnull
Registered: Wed Jun 12 09:55:16 UTC 2024 - Last Modified: Mon May 13 09:53:45 UTC 2024 - 6.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390X.rules
(F(CMP|CMPS) x (FMOV(D|S)const [0.0])) => (LT(D|E)BR x) (F(CMP|CMPS) (FMOV(D|S)const [0.0]) x) => (InvertFlags (LT(D|E)BR <v.Type> x)) // FSUB, FSUBS, FADD, FADDS now produce a condition code representing the // comparison of the result with 0.0. If a compare with zero instruction // (e.g. LTDBR) is following one of those instructions, we can use the
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 12 18:09:26 UTC 2023 - 74.3K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/list7.go
if spc >= SPOP_BEGIN && spc < SPOP_END { return fmt.Sprintf("%s", spc) } return "SPC_??" } func rlconv(list int64) string { str := "" // ARM64 register list follows ARM64 instruction decode schema // | 31 | 30 | ... | 15 - 12 | 11 - 10 | ... | // +----+----+-----+---------+---------+-----+ // | | Q | ... | opcode | size | ... | firstReg := int(list & 31)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 6K bytes - Viewed (0)