// function adjusted by i.
// On x86 and amd64, runtime.callbackasm is a series of CALL instructions,
// and we want callback to arrive at
// correspondent call instruction instead of start of
// runtime.callbackasm.
// On ARM, runtime.callbackasm is a series of mov and branch instructions.
// R12 is loaded with the callback index. Each entry is two instructions,
// hence 8 bytes.
func callbackasmAddr(i int) uintptr {
	var entrySize int

// tracking for small regular expressions and texts. It allocates
// a bit vector with (length of input) * (length of prog) bits,
// to make sure it never explores the same (character position, instruction)
// state multiple times. This limits the search to run in time linear in
// the length of the test.
//
// backtrack is a fast replacement for the NFA code on small
// regexps when onepass cannot be used.

	AAMMINDBWU
	AAMMINDBVU

	// 2.2.10. Other Miscellaneous Instructions
	ARDTIMELW
	ARDTIMEHW
	ARDTIMED

	ALAST

	// aliases
	AJMP = obj.AJMP
	AJAL = obj.ACALL
	ARET = obj.ARET
)

func init() {
	// The asm encoder generally assumes that the lowest 5 bits of the
	// REG_XX constants match the machine instruction encoding, i.e.
	// the lowest 5 bits is the register number.

	pcdata.To.Type = TYPE_CONST
	pcdata.To.Offset = oldval

	return pcdata
}

// MarkUnsafePoints inserts PCDATAs to mark nonpreemptible and restartable
// instruction sequences, based on isUnsafePoint and isRestartable predicate.
// p0 is the start of the instruction stream.
// isUnsafePoint(p) returns true if p is not safe for async preemption.
// isRestartable(p) returns true if we can restart at the start of p (this Prog)

	arch := sys.ArchAMD64

	theArch := ld.Arch{
		Funcalign:  funcAlign,
		Maxalign:   maxAlign,
		Minalign:   minAlign,
		Dwarfregsp: dwarfRegSP,
		Dwarfreglr: dwarfRegLR,
		// 0xCC is INT $3 - breakpoint instruction
		CodePad: []byte{0xCC},

		Plan9Magic:  uint32(4*26*26 + 7),
		Plan9_64Bit: true,

		Adddynrel:        adddynrel,
		Archinit:         archinit,
		Archreloc:        archreloc,

	case AMRC:
		if p.To.Offset&0xffff0fff == 0xee1d0f70 {
			// Because the instruction might be rewritten to a BL which returns in R0
			// the register must be zero.
			if p.To.Offset&0xf000 != 0 {
				ctxt.Diag("%v: TLS MRC instruction must write to R0 as it might get translated into a BL instruction", p.Line())
			}

			if buildcfg.GOARM.Version < 7 {

	{i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
	{i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},

	// undefined (deliberate illegal instruction)
	{i: 78, as: obj.AUNDEF},

	// Break point instruction(0x0001 opcode)
	{i: 73, as: ABRRK},

	// 2 byte no-operation
	{i: 66, as: ANOPH},

	// crypto instructions

	// KM
	{i: 124, as: AKM, a1: C_REG, a6: C_REG},

	// KDSA
	{i: 125, as: AKDSA, a1: C_REG, a6: C_REG},

	MOVB	c+16(FP), AL
	LEAQ	ret+24(FP), R8
	JMP	countbody<>(SB)

// input:
//   SI: data
//   BX: data len
//   AL: byte sought
//   R8: address to put result
// This function requires the POPCNT instruction.
TEXT countbody<>(SB),NOSPLIT,$0
	// Shuffle X0 around so that each byte contains
	// the character we're looking for.
	MOVD AX, X0
	PUNPCKLBW X0, X0
	PUNPCKLBW X0, X0
	PSHUFL $0, X0, X0

	CMPQ BX, $16

	cpu.*: cpu.all=off disables the use of all optional instruction set extensions.
	cpu.extension=off disables use of instructions from the specified instruction set extension.
	extension is the lower case name for the instruction set extension such as sse41 or avx
	as listed in internal/cpu package. As an example cpu.avx=off disables runtime detection
	and thereby use of AVX instructions.

	cgocheck: setting cgocheck=0 disables all checks for packages

type inlinedCall struct {
	funcID    abi.FuncID // type of the called function
	_         [3]byte
	nameOff   int32 // offset into pclntab for name of called function
	parentPc  int32 // position of an instruction whose source position is the call site (offset from entry)
	startLine int32 // line number of start of function (func keyword/TEXT directive)
}

// An inlineUnwinder iterates over the stack of inlined calls at a PC by