ENOPROTOOPT        = Errno(1109)
	EPROTONOSUPPORT    = Errno(1110)
	ESOCKTNOSUPPORT    = Errno(1111)
	EOPNOTSUPP         = Errno(1112)
	EPFNOSUPPORT       = Errno(1113)
	EAFNOSUPPORT       = Errno(1114)
	EADDRINUSE         = Errno(1115)
	EADDRNOTAVAIL      = Errno(1116)
	ENETDOWN           = Errno(1117)
	ENETUNREACH        = Errno(1118)
	ENETRESET          = Errno(1119)
	ECONNABORTED       = Errno(1120)

				// BEQZ/BNEZ can be encoded with 21-bit offsets.
				width = 21
				as = -as
				if rj == 0 || rj == REGZERO {
					rj = rd
				}
			}
		}
		switch width {
		case 21:
			if (v<<11)>>11 != v {
				c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
			}
			o1 = OP_16IR_5I(c.opirr(as), uint32(v), uint32(rj))
		case 16:
			if (v<<16)>>16 != v {

	AMRET
	ASRET
	ADRET

	// 3.2.3: Wait for Interrupt
	AWFI

	// 4.2.1: Supervisor Memory-Management Fence Instruction
	ASFENCEVMA

	//
	// RISC-V Bit-Manipulation ISA-extensions (1.0)
	//

	// 1.1: Address Generation Instructions (Zba)
	AADDUW
	ASH1ADD
	ASH1ADDUW
	ASH2ADD
	ASH2ADDUW
	ASH3ADD
	ASH3ADDUW
	ASLLIUW

	// 1.2: Basic Bit Manipulation (Zbb)
	AANDN
	AORN

	case 54: /* floating point arith */
		o1 = c.oprrr(p, p.As)
		rf := int(p.From.Reg)
		rt := int(p.To.Reg)
		r := int(p.Reg)
		if (o1&(0x1F<<24)) == (0x1E<<24) && (o1&(1<<11)) == 0 { /* monadic */
			r = rf
			rf = 0
		} else if r == obj.REG_NONE {
			r = rt
		}
		o1 |= (uint32(rf&31) << 16) | (uint32(r&31) << 5) | uint32(rt&31)

	case 55: /* floating-point constant */

	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
}

/* VX-form 2-register operands, r/none/r */
func AOP_RR(op uint32, d uint32, a uint32) uint32 {
	return op | (d&31)<<21 | (a&31)<<11
}

/* VA-form 4-register operands */
func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
	return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
}

depending on the type argument for <code>f</code>.
Accordingly, if <code>f</code> is instantiated with a <code>float32</code> type,
the numeric value of the expression <code>P(1.1) + 1.2</code> will be computed
with the same precision as the corresponding non-constant <code>float32</code>
addition.
</p>

<p>
A non-constant value <code>x</code> can be converted to type <code>T</code>

	// if r3 is not zero (failed) then branch to finish
	BYTE $0xB9; BYTE $0x02; BYTE $0x00; BYTE $0x33 // lbl1     ltgr  3,3
	BYTE $0xA7; BYTE $0x74; BYTE $0x00; BYTE $0x08 // brc   b'0111',lbl2

	// stomic store shunt address in R5 into CEECAADMC
	BYTE $0xE3; BYTE $0x52; BYTE $0x00; BYTE $0x00; BYTE $0x00; BYTE $0x24 // stg   5,0(2)

	FNMADDD	F1, F2, F3, F4				// 4f82201a

	// 12.6: Double-Precision Floating-Point Classify Instruction
	FCLASSD	F0, X5					// d31200e2

	// RISC-V Bit-Manipulation ISA-extensions (1.0)
	// 1.1: Address Generation Instructions (Zba)
	ADDUW		X10, X11, X12			// 3b86a508
	ADDUW		X10, X11			// bb85a508
	SH1ADD		X11, X12, X13			// b326b620
	SH1ADD		X11, X12			// 3326b620
	SH1ADDUW	X12, X13, X14			// 3ba7c620

	// overflow, the 20 top bits would be 1, and the sign bit for
	// the low 12 bits would be set, in which case the entire 32
	// bit pattern fits in a 12 bit signed value.
	if imm&(1<<11) != 0 {
		high++
	}

	low = signExtend(imm, 12)
	high = signExtend(high, 20)

	return low, high, nil
}

func regVal(r, min, max uint32) uint32 {
	if r < min || r > max {