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Results 181 - 182 of 182 for Gleason (0.09 sec)

  1. src/cmd/compile/internal/ssa/regalloc.go

    		}
    		s.setOrig(c, v2)
    		s.assignReg(r2, v2, c)
    	}
    
    	// If the evicted register isn't used between the start of the block
    	// and now then there is no reason to even request it on entry. We can
    	// drop from startRegs in that case.
    	if s.usedSinceBlockStart&(regMask(1)<<r) == 0 {
    		if s.startRegsMask&(regMask(1)<<r) == 1 {
    			if s.f.pass.debug > regDebug {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 17:49:56 UTC 2023
    - 87.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    // Commenting out for now, because it also can't trigger because of the is32bit guard on the
    // ANDQconst lowering-rule, above, prevents 0xFFFFFFFF from matching (for the same reason)
    // Using an alternate form of this rule segfaults some binaries because of
    // adverse interactions with other passes.
    // (ANDQconst [0xFFFFFFFF] x) => (MOVLQZX x)
    
    // strength reduction
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
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