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Results 31 - 39 of 39 for MASK (0.04 sec)
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src/net/netip/netip_test.go
bits: 20, p: mustPrefix("255.255.240.0/20"), ok: true, }, { // Partially masking one byte that contains both // 1s and 0s on either side of the mask limit. ip: mustIP("100.98.156.66"), bits: 10, p: mustPrefix("100.64.0.0/10"), ok: true, }, }, }, { family: "IPv6", subtests: makeIPv6(""),
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 04 17:10:01 UTC 2024 - 54.3K bytes - Viewed (0) -
src/time/format.go
stdSeparatorShift = 28 // extra argument in high 4 bits for fractional second separators stdMask = 1<<stdArgShift - 1 // mask out argument ) // std0x records the std values for "01", "02", ..., "06". var std0x = [...]int{stdZeroMonth, stdZeroDay, stdZeroHour12, stdZeroMinute, stdZeroSecond, stdYear}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 11 17:09:28 UTC 2024 - 49.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/prove.go
// arbitrary number so we can't list them all here. jumpTable0 ) // relation represents the set of possible relations between // pairs of variables (v, w). Without a priori knowledge the // mask is lt | eq | gt meaning v can be less than, equal to or // greater than w. When the execution path branches on the condition // `v op w` the set of relations is updated to exclude any
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:30:21 UTC 2024 - 48.9K bytes - Viewed (0) -
src/runtime/traceback.go
} bits := *(*uint8)(add(liveInfo, uintptr(liveIdx)+uintptr(slotIdx/8))) return bits&(1<<(slotIdx%8)) != 0 } print1 := func(off, sz, slotIdx uint8) { x := readUnaligned64(add(argp, uintptr(off))) // mask out irrelevant bits if sz < 8 { shift := 64 - sz*8 if goarch.BigEndian { x = x >> shift } else { x = x << shift >> shift } } print(hex(x)) if !isLive(off, slotIdx) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 29 16:25:21 UTC 2024 - 55.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/ir/tf_ops.td
If `x` and `y` are vectors or higher rank, then `condition` must be either a scalar, a vector with size matching the first dimension of `x`, or must have the same shape as `x`. The `condition` tensor acts as a mask that chooses, based on the value at each element, whether the corresponding element / row in the output should be taken from `x` (if true) or `y` (if false).
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Apr 24 04:08:35 UTC 2024 - 90.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(RotateLeft(32|64) ...) => ((ROTLW|ROTL) ...) // Constant rotate generation (ROTLW x (MOVDconst [c])) => (ROTLWconst x [c&31]) (ROTL x (MOVDconst [c])) => (ROTLconst x [c&63]) // Combine rotate and mask operations (ANDconst [m] (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x) (AND (MOVDconst [m]) (ROTLWconst [r] x)) && isPPC64WordRotateMask(m) => (RLWINM [encodePPC64RotateMask(r,m,32)] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/runtime/asm_amd64.s
AESENC runtime·aeskeysched+16(SB), X0 AESENC runtime·aeskeysched+32(SB), X0 MOVQ X0, AX // return X0 RET noaes: JMP runtime·memhash64Fallback<ABIInternal>(SB) // simple mask to get rid of data in the high part of the register. DATA masks<>+0x00(SB)/8, $0x0000000000000000 DATA masks<>+0x08(SB)/8, $0x0000000000000000 DATA masks<>+0x10(SB)/8, $0x00000000000000ff
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sat May 11 20:38:24 UTC 2024 - 60.4K bytes - Viewed (0) -
src/cmd/vendor/github.com/ianlancetaylor/demangle/demangle.go
// the parsing of the AST, only the conversion of the AST // to a string. LLVMStyle ) // maxLengthShift is how we shift the MaxLength value. const maxLengthShift = 16 // maxLengthMask is a mask for the maxLength value. const maxLengthMask = 0x1f << maxLengthShift // MaxLength returns an Option that limits the maximum length of a // demangled string. The maximum length is expressed as a power of 2,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 31 19:48:28 UTC 2024 - 94.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
// generic.rules changes ANDs of high-part/low-part masks into a couple of shifts, // for instance: // x & 0xFFFF0000 -> (x >> 16) << 16 // x & 0x80000000 -> (x >> 31) << 31 // // In case the mask is just one bit (like second example above), it conflicts // with the above rules to detect bit-testing / bit-clearing of first/last bit. // We thus special-case them, by detecting the shift patterns.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0)