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Results 1 - 3 of 3 for opcodeTable (0.14 sec)
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src/cmd/compile/internal/ssa/regalloc.go
} if op.IsCall() { if ac, ok := v.Aux.(*AuxCall); ok && ac.reg != nil { return *ac.Reg(&opcodeTable[op].reg, s.f.Config) } } if op == OpMakeResult && s.f.OwnAux.reg != nil { return *s.f.OwnAux.ResultReg(s.f.Config) } return opcodeTable[op].reg } func (s *regAllocState) isGReg(r register) bool { return s.f.Config.hasGReg && s.GReg == r }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 17:49:56 UTC 2023 - 87.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/debug.go
state.currentState.slots[slot] = loc } // Handle any register clobbering. Call operations, for example, // clobber all registers even though they don't explicitly write to // them. clobbers := uint64(opcodeTable[v.Op].reg.clobbers) for { if clobbers == 0 { break } reg := uint8(bits.TrailingZeros64(clobbers)) clobbers &^= 1 << reg for _, slot := range locs.registers[reg] {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jun 10 19:44:43 UTC 2024 - 58.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite.go
return false } baseAndOffset := func(ptr *Value) (base *Value, offset int64) { base, offset = ptr, 0 for base.Op == OpOffPtr { offset += base.AuxInt base = base.Args[0] } if opcodeTable[base.Op].nilCheck { base = base.Args[0] } return base, offset } p1, off1 := baseAndOffset(p1) p2, off2 := baseAndOffset(p2) if isSamePtr(p1, p2) { return !overlap(off1, n1, off2, n2) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 64.2K bytes - Viewed (0)