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okhttp/src/test/resources/okhttp3/internal/publicsuffix/public_suffix_list.dat
k8s.fr-par.scw.cloud nodes.k8s.fr-par.scw.cloud s3.fr-par.scw.cloud s3-website.fr-par.scw.cloud whm.fr-par.scw.cloud priv.instances.scw.cloud pub.instances.scw.cloud k8s.scw.cloud k8s.nl-ams.scw.cloud nodes.k8s.nl-ams.scw.cloud s3.nl-ams.scw.cloud s3-website.nl-ams.scw.cloud whm.nl-ams.scw.cloud k8s.pl-waw.scw.cloud nodes.k8s.pl-waw.scw.cloud s3.pl-waw.scw.cloud
Registered: Sun Jun 16 04:42:17 UTC 2024 - Last Modified: Wed Dec 20 23:27:07 UTC 2023 - 240.3K bytes - Viewed (0) -
src/cmd/go/internal/work/exec.go
sum := sha256.Sum256([]byte(a.Package.ImportPath)) coverVar := fmt.Sprintf("goCover_%x_", sum[:6]) mode := a.Package.Internal.Cover.Mode if mode == "" { panic("covermode should be set at this point") } if newoutfiles, err := b.cover2(a, infiles, outfiles, coverVar, mode); err != nil { return err } else { outfiles = newoutfiles
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jun 10 14:46:37 UTC 2024 - 105.6K bytes - Viewed (0) -
src/cmd/internal/obj/x86/asm6.go
bytereg(&p.To, &p.Tt) } case P32: // 32 bit but illegal if 64-bit mode if ctxt.Arch.Family == sys.AMD64 { ctxt.Diag("asmins: illegal in 64-bit mode: %v", p) } case Py: // 64-bit only, no prefix if ctxt.Arch.Family != sys.AMD64 { ctxt.Diag("asmins: illegal in %d-bit mode: %v", ctxt.Arch.RegSize*8, p) } case Py1: // 64-bit only if z < 1, no prefix
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/ir/tfl_ops.cc
// regardless of dimension size. if (!has_unknown_shape_input) { return has_same_shape || max_rank <= max_bcast_rank; } // It will treat the unknown shape inputs as acceptable inputs for model // compatibility if all known ranks are no bigger than the allowed broadcast // maximum rank. if (max_rank <= max_bcast_rank) { return true; }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 169.2K bytes - Viewed (0) -
pkg/scheduler/internal/queue/scheduling_queue_test.go
if err != nil { t.Fatalf("unexpected error from AddUnschedulableIfNotPresent: %v", err) } expectInFlightPods(t, q) // This NodeAdd event moves unschedulablePodInfo and highPriorityPodInfo to the backoffQ, // because of the queueing hint function registered for NodeAdd/fooPlugin. q.MoveAllToActiveOrBackoffQueue(logger, NodeAdd, nil, nil, nil)
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Wed Jun 12 13:26:09 UTC 2024 - 146.9K bytes - Viewed (0) -
platforms/software/dependency-management/src/integTest/groovy/org/gradle/integtests/resolve/transform/ArtifactTransformIntegrationTest.groovy
output.count("Transforming") == 0 } @ToBeFixedForConfigurationCache(because = "task that uses file collection containing transforms but does not declare this as an input may be encoded before the transform nodes it references") def "transforms are created as required and a new instance created for each file"() { given: buildFile << """ dependencies { compile project(':lib')
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Tue Nov 07 18:43:42 UTC 2023 - 100.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) => (FMOVSstore [off] {sym} ptr val mem) (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem) // float <=> int register moves, with no conversion. // These come up when compiling math.{Float64bits, Float64frombits, Float32bits, Float32frombits}. (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) => (FMOVDfpgp val)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/extract_outside_compilation.mlir
return } } // ----- // Tests that model parallelism does not affect outside compilation.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Oct 31 08:59:10 UTC 2023 - 129.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/ir/tf_ops_a_m.cc
// FusedBatchNorm in training mode is a layout sentitive operation, and should // have already assigned an optimal data format. if (op->getIsTraining()) return failure(); return ::mlir::TF::FoldOperandsPermutation(permutation, op); } template <class Op> static StringRef GetOptimalLayout(const RuntimeDevices& devices, Op* op) { // In inference mode FusedBatchNorm is not sensitive to data layout.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 146.7K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
break } mode := 64 v := uint64(p.From.Offset) switch p.As { case AANDW, AORRW, AEORW, AANDSW, ATSTW: mode = 32 case ABIC, AORN, AEON, ABICS: v = ^v case ABICW, AORNW, AEONW, ABICSW: v = ^v mode = 32 } o1 = c.opirr(p, a) o1 |= bitconEncode(v, mode) | uint32(r&31)<<5 | uint32(rt&31)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0)