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Results 21 - 30 of 43 for Shift3 (0.28 sec)
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staging/src/k8s.io/api/storage/v1beta1/generated.pb.go
iNdEx := 0 for iNdEx < l { preIndex := iNdEx var wire uint64 for shift := uint(0); ; shift += 7 { if shift >= 64 { return ErrIntOverflowGenerated } if iNdEx >= l { return io.ErrUnexpectedEOF } b := dAtA[iNdEx] iNdEx++ wire |= uint64(b&0x7F) << shift if b < 0x80 { break } } fieldNum := int32(wire >> 3)
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Fri Mar 01 06:06:37 UTC 2024 - 133.9K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/tables.go
// CMN <Wn|WSP>, #<imm>{, <shift>} {0xff00001f, 0x3100001f, CMN, instArgs{arg_Wns, arg_IAddSub}, nil}, // ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>} {0xff000000, 0x31000000, ADDS, instArgs{arg_Wd, arg_Wns, arg_IAddSub}, nil}, // CMN <Xn|SP>, #<imm>{, <shift>} {0xff00001f, 0xb100001f, CMN, instArgs{arg_Xns, arg_IAddSub}, nil}, // ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 211.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
// S{HL, HR, AR}x: shift operations // SHL: shift left // SHR: shift right logical (0s are shifted in from beyond the word size) // SAR: shift right arithmetic (sign bit is shifted in from beyond the word size) // arg0 is the value being shifted // arg1 is the amount to shift, interpreted mod (Q=64,L=32,W=32,B=32) // (Note: x86 is weird, the 16 and 8 byte shifts still use all 5 bits of shift amount!)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json
{"Name":"BIC (shifted register)","Bits":"0|0|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BIC <Wd>, <Wn>, <Wm>{, <shift> #<amount>}","Code":"","Alias":""}, {"Name":"BIC (shifted register)","Bits":"1|0|0|0|1|0|1|0|shift:2|1|Rm:5|imm6:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BIC <Xd>, <Xn>, <Xm>{, <shift> #<amount>}","Code":"","Alias":""},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 234.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/generic.rules
// Non-constant rotate detection. // We use shiftIsBounded to make sure that neither of the shifts are >64. // Note: these rules are subtle when the shift amounts are 0/64, as Go shifts // are different from most native shifts. But it works out.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 16 22:21:05 UTC 2024 - 135.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(Not x) => (XOR (MOVDconst [1]) x) // shifts // hardware instruction uses only the low 6 bits of the shift // we compare to 64 to ensure Go semantics for large shifts // Rules about rotates with non-const shift are based on the following rules, // if the following rules change, please also modify the rules based on them. // check shiftIsBounded first, if shift value is proved to be valid then we // can do the shift directly.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/asmz.go
op_SRA uint32 = 0x8A00 // FORMAT_RS1 SHIFT RIGHT SINGLE (32) op_SRAG uint32 = 0xEB0A // FORMAT_RSY1 SHIFT RIGHT SINGLE (64) op_SRAK uint32 = 0xEBDC // FORMAT_RSY1 SHIFT RIGHT SINGLE (32) op_SRDA uint32 = 0x8E00 // FORMAT_RS1 SHIFT RIGHT DOUBLE op_SRDL uint32 = 0x8C00 // FORMAT_RS1 SHIFT RIGHT DOUBLE LOGICAL op_SRDT uint32 = 0xED41 // FORMAT_RXF SHIFT SIGNIFICAND RIGHT (long DFP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 176.7K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/asm7.go
is64bit := o1 & (1 << 31) if is64bit == 0 && amount >= 32 { c.ctxt.Diag("shift amount out of range 0 to 31: %v", p) } shift := (p.From.Offset >> 22) & 3 if (shift > 2 || shift < 0) && (isADDop(p.As) || isADDWop(p.As) || isNEGop(p.As)) { c.ctxt.Diag("unsupported shift operator: %v", p) } o1 |= uint32(p.From.Offset) /* includes reg, op, etc */ rt := int(p.To.Reg)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
doc/go1.17_spec.html
a <a href="#Run_time_panics">run-time panic</a> occurs. The shift operators implement arithmetic shifts if the left operand is a signed integer and logical shifts if it is an unsigned integer. There is no upper limit on the shift count. Shifts behave as if the left operand is shifted <code>n</code> times by 1 for a shift count of <code>n</code>.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 11 20:22:45 UTC 2024 - 211.6K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
/* Vector shift */ {as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector shift, vx-form */ {as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4}, /* vector shift algebraic, vx-form */ {as: AVSOI, a1: C_U16CON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector shift by octet immediate, va-form */ /* Vector count */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0)