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tensorflow/compiler/mlir/tensorflow/transforms/tf_passes.td
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Jun 12 21:18:05 UTC 2024 - 99.6K bytes - Viewed (0) -
src/cmd/internal/obj/x86/asm6.go
ycover[Yu8*Ymax+Yi32] = 1 ycover[Yi8*Ymax+Yi32] = 1 ycover[Ys32*Ymax+Yi32] = 1 ycover[Yi0*Ymax+Yi64] = 1 ycover[Yi1*Ymax+Yi64] = 1 ycover[Yu7*Ymax+Yi64] = 1 ycover[Yu2*Ymax+Yi64] = 1 ycover[Yu8*Ymax+Yi64] = 1 ycover[Yi8*Ymax+Yi64] = 1 ycover[Ys32*Ymax+Yi64] = 1 ycover[Yi32*Ymax+Yi64] = 1 ycover[Yal*Ymax+Yrb] = 1 ycover[Ycl*Ymax+Yrb] = 1 ycover[Yax*Ymax+Yrb] = 1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/ops.mlir
} // CHECK-LABEL: testSubInt64 func.func @testSubInt64(tensor<? x i64>, tensor<? x i64>) -> tensor<? x i64> { ^bb0(%arg0: tensor<? x i64>, %arg1: tensor<? x i64>): // CHECK: tfl.sub %arg0, %arg1 {fused_activation_function = "RELU6"} %0 = tfl.sub %arg0, %arg1 {fused_activation_function = "RELU6"} : tensor<? x i64> func.return %0#0 : tensor<? x i64> } // CHECK-LABEL: testMul
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Jun 06 19:09:08 UTC 2024 - 189.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/tpu_rewrite.mlir
%read1 = "tf.ReadVariableOp"(%arg1) : (tensor<!tf_type.resource<tensor<i32>>>) -> tensor<i32> // CHECK-NOT: tf.TPUPartitionedInputV2 %partitioned_input = "tf.TPUPartitionedInputV2"(%read0, %read1) {N = 2 : i64, partition_dims = []} : (tensor<i32>, tensor<i32>) -> tensor<i32> // CHECK: %[[COMPILE_OUTPUT:[0-9]*]]:3 = "tf_device.launch" // CHECK-NEXT: "tf._TPUCompileMlir"() // CHECK: "tf_device.launch"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 22:03:30 UTC 2024 - 172.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/transforms/uniform_quantized_stablehlo_to_tfl_pass.cc
return rewriter.create<TFL::QConstOp>( loc, /*output=*/TypeAttr::get(bias_type), /*value=*/bias_value); } // Casts the given op shapes from i64 to i32 to fit TFLite spec requirement. arith::ConstantOp CreateI32ShapeConstantOp(const TensorType op_type, const Location loc,
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Apr 22 09:00:19 UTC 2024 - 99.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/generic.rules
// ((x >> c1) << c2) >> c3 (Rsh(64|32|16|8)Ux64 (Lsh(64|32|16|8)x64 (Rsh(64|32|16|8)Ux64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3])) && uint64(c1) >= uint64(c2) && uint64(c3) >= uint64(c2) && !uaddOvf(c1-c2, c3) => (Rsh(64|32|16|8)Ux64 x (Const64 <typ.UInt64> [c1-c2+c3])) // ((x << c1) >> c2) << c3 (Lsh(64|32|16|8)x64 (Rsh(64|32|16|8)Ux64 (Lsh(64|32|16|8)x64 x (Const64 [c1])) (Const64 [c2])) (Const64 [c3]))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 16 22:21:05 UTC 2024 - 135.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/transforms/optimize.cc
// for each dim i, the output tensor is identical to `input`. bool CanOptimizeIdentitySliceOp(Value input, Attribute begin, Attribute size) { // Checks if `begin` and `size` are i32 or i64. auto begin_attr = mlir::dyn_cast<DenseIntElementsAttr>(begin); auto size_attr = mlir::dyn_cast<DenseIntElementsAttr>(size); if (!begin_attr || !size_attr) { return false; }
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Apr 30 00:40:15 UTC 2024 - 102.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/ir/tfl_ops.cc
} // Return true when the given element_type is UI32. bool IsUI32Type(Type element_type) { return element_type.isInteger(32) && element_type.isUnsignedInteger(); } // Return true when the given element_type is I64. bool IsI64Type(Type element_type) { return element_type.isInteger(64) && !element_type.isUnsignedInteger(); } // Return true if the value is a splat tensor constant zero. bool EqualsZero(Value value) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 169.2K bytes - Viewed (0)