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Results 1 - 7 of 7 for vmov (0.05 sec)
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src/cmd/internal/obj/arm64/asm7.go
{AVMOV, C_ELEM, C_NONE, C_NONE, C_ZREG, C_NONE, 73, 4, 0, 0, 0}, {AVMOV, C_ELEM, C_NONE, C_NONE, C_ELEM, C_NONE, 92, 4, 0, 0, 0}, {AVMOV, C_ELEM, C_NONE, C_NONE, C_VREG, C_NONE, 80, 4, 0, 0, 0}, {AVMOV, C_ZREG, C_NONE, C_NONE, C_ARNG, C_NONE, 82, 4, 0, 0, 0}, {AVMOV, C_ZREG, C_NONE, C_NONE, C_ELEM, C_NONE, 78, 4, 0, 0, 0}, {AVMOV, C_ARNG, C_NONE, C_NONE, C_ARNG, C_NONE, 83, 4, 0, 0, 0},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 201.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/tables.go
{0xfffffc00, 0x9e660000, FMOV, instArgs{arg_Xd, arg_Dn}, nil}, // FMOV <Xd>, <Vn>.D[1] {0xfffffc00, 0x9eae0000, FMOV, instArgs{arg_Xd, arg_Vn_arrangement_D_index__1}, nil}, // FMOV <Sd>, <Sn> {0xfffffc00, 0x1e204000, FMOV, instArgs{arg_Sd, arg_Sn}, nil}, // FMOV <Dd>, <Dn> {0xfffffc00, 0x1e604000, FMOV, instArgs{arg_Dd, arg_Dn}, nil}, // FMOV <Sd>, #<imm>
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 211.8K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/inst.json
{"Name":"FMOV (register)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Dd>, <Dn>","Code":"","Alias":""}, {"Name":"FMOV (general)","Bits":"0|0|0|1|1|1|1|0|00:2|1|00:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"FMOV <Sd>, <Wn>","Code":"","Alias":""},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Aug 16 17:57:48 UTC 2017 - 234.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
{name: "CMOVWCS", argLength: 3, reg: gp21, asm: "CMOVWCS", resultInArg0: true}, // CMOV with floating point instructions. We need separate pseudo-op to handle // InvertFlags correctly, and to generate special code that handles NaN (unordered flag). // NOTE: the fact that CMOV*EQF here is marked to generate CMOV*NE is not a bug. See // code generation in amd64/ssa.go.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(GreaterEqualNoov (InvertFlags x)) => (CSINC [OpARM64NotEqual] (LessThanNoov <typ.Bool> x) (MOVDconst [0]) x) // Don't bother extending if we're not using the higher bits. (MOV(B|BU)reg x) && v.Type.Size() <= 1 => x (MOV(H|HU)reg x) && v.Type.Size() <= 2 => x (MOV(W|WU)reg x) && v.Type.Size() <= 4 => x // omit sign extension (MOVWreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffff80000000) == 0 => (ANDconst <t> x [c])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
okhttp/src/test/resources/okhttp3/internal/publicsuffix/public_suffix_list.dat
moscow // moto : 2015-06-04 Motorola Trademark Holdings, LLC moto // motorcycles : 2014-01-09 XYZ.COM LLC motorcycles // mov : 2014-01-30 Charleston Road Registry Inc. mov // movie : 2015-02-05 Binky Moon, LLC movie // msd : 2015-07-23 MSD Registry Holdings, Inc. msd // mtn : 2014-12-04 MTN Dubai Limited mtn
Registered: Sun Jun 16 04:42:17 UTC 2024 - Last Modified: Wed Dec 20 23:27:07 UTC 2023 - 240.3K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/asmz.go
case 62: // equivalent of Mul64 in math/bits zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm) case 66: zRR(op_BCR, uint32(Never), 0, asm) case 67: // fmov $0 freg var opcode uint32 switch p.As { case AFMOVS: opcode = op_LZER case AFMOVD: opcode = op_LZDR } zRRE(opcode, uint32(p.To.Reg), 0, asm) case 68: // movw areg reg
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 176.7K bytes - Viewed (0)