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staging/src/k8s.io/api/autoscaling/v2beta2/generated.pb.go
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Fri Mar 01 06:06:37 UTC 2024 - 163K bytes - Viewed (0) -
staging/src/k8s.io/api/autoscaling/v2beta1/generated.pb.go
iNdEx = postIndex default: iNdEx = preIndex skippy, err := skipGenerated(dAtA[iNdEx:]) if err != nil { return err } if (skippy < 0) || (iNdEx+skippy) < 0 { return ErrInvalidLengthGenerated } if (iNdEx + skippy) > l { return io.ErrUnexpectedEOF } iNdEx += skippy } } if iNdEx > l { return io.ErrUnexpectedEOF }
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Fri Mar 01 06:06:37 UTC 2024 - 142.9K bytes - Viewed (0) -
pkg/controller/job/job_controller_test.go
buildPod().phase(v1.PodSucceeded).index("0").Pod, buildPod().phase(v1.PodFailed).index("1").Pod, buildPod().phase(v1.PodSucceeded).trackingFinalizer().index("1").Pod, buildPod().phase(v1.PodSucceeded).trackingFinalizer().index("3").Pod, buildPod().uid("a").phase(v1.PodFailed).trackingFinalizer().index("2").Pod, buildPod().uid("b").phase(v1.PodFailed).trackingFinalizer().index("5").Pod, }, wantRmFinalizers: 4,
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Tue Jun 11 15:36:36 UTC 2024 - 229.2K bytes - Viewed (0) -
tensorflow/c/c_api.cc
if (ic->num_outputs() <= new_src.index) { status->status = tensorflow::errors::OutOfRange( "Cannot update edge. Output index [", new_src.index, "] is greater than the number of total outputs [", ic->num_outputs(), "]."); return; } tensorflow::shape_inference::ShapeHandle shape = ic->output(new_src.index); tensorflow::shape_inference::InferenceContext* ic_dst =
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Apr 15 03:35:10 UTC 2024 - 102.3K bytes - Viewed (0) -
tensorflow/compiler/jit/extract_outside_compilation_pass.cc
for (auto* n : ret_nodes) { int index; TF_RETURN_IF_ERROR(GetNodeAttr(n->attrs(), "index", &index)); const int num_dtypes = send_from_host_dtypes.size(); if (index < 0 || index >= num_dtypes) { return errors::Internal("Invalid _Retval index: ", index); } for (auto edge : n->in_edges()) { inputs[index] =
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Mar 12 06:33:33 UTC 2024 - 104.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/translate/import_model.cc
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed May 01 11:17:36 UTC 2024 - 183.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/flatbuffer_export.cc
BufferOffset<tflite::Buffer> empty_buffer_; std::vector<BufferOffset<tflite::Buffer>> buffers_; // Maps subgraph index and tensor name in the graph to the tensor index. absl::flat_hash_map<int, absl::flat_hash_map<std::string, int>> tensor_index_map_; // Maps op name to index of the corresponding OperatorCode in opcodes_ vector. absl::flat_hash_map<std::string, uint32_t> opcode_index_map_;
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Jun 12 21:41:49 UTC 2024 - 164.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/ir/tf_ops_n_z.cc
} // Checks if the `index` bit of `val` is set. template <class T> constexpr bool IsSet(const T &val, unsigned index) { return (val & (1 << index)) != 0; } // Sets the `index` bit of `val`. template <class T> constexpr void Set(T &val, unsigned index) { val |= (1 << index); } // Unset the `index` bit of `val`. template <class T>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 09 22:07:10 UTC 2024 - 170.8K bytes - Viewed (0) -
guava/src/com/google/common/cache/LocalCache.java
preWriteCleanup(now); int newCount = this.count - 1; AtomicReferenceArray<ReferenceEntry<K, V>> table = this.table; int index = hash & (table.length() - 1); ReferenceEntry<K, V> first = table.get(index); for (e = first; e != null; e = e.getNext()) { K entryKey = e.getKey(); if (e.getHash() == hash && entryKey != null
Registered: Wed Jun 12 16:38:11 UTC 2024 - Last Modified: Sat May 18 03:24:34 UTC 2024 - 149.2K bytes - Viewed (0) -
src/cmd/internal/obj/x86/asm6.go
func avx2gatherValid(ctxt *obj.Link, p *obj.Prog) bool { // If any pair of the index, mask, or destination registers // are the same, illegal instruction trap (#UD) is triggered. index := regIndex(p.GetFrom3().Index) mask := regIndex(p.From.Reg) dest := regIndex(p.To.Reg) if dest == mask || dest == index || mask == index { ctxt.Diag("mask, index, and destination registers should be distinct: %v", p) return false }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0)