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Results 1 - 9 of 9 for Shift2 (0.28 sec)

  1. src/cmd/compile/internal/ssa/_gen/generic.rules

    // Non-constant rotate detection.
    // We use shiftIsBounded to make sure that neither of the shifts are >64.
    // Note: these rules are subtle when the shift amounts are 0/64, as Go shifts
    // are different from most native shifts. But it works out.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 16 22:21:05 UTC 2024
    - 135.3K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (Not    x) => (XOR (MOVDconst [1]) x)
    
    // shifts
    // hardware instruction uses only the low 6 bits of the shift
    // we compare to 64 to ensure Go semantics for large shifts
    // Rules about rotates with non-const shift are based on the following rules,
    // if the following rules change, please also modify the rules based on them.
    
    // check shiftIsBounded first, if shift value is proved to be valid then we
    // can do the shift directly.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/arm64/asm7.go

    		is64bit := o1 & (1 << 31)
    		if is64bit == 0 && amount >= 32 {
    			c.ctxt.Diag("shift amount out of range 0 to 31: %v", p)
    		}
    		shift := (p.From.Offset >> 22) & 3
    		if (shift > 2 || shift < 0) && (isADDop(p.As) || isADDWop(p.As) || isNEGop(p.As)) {
    			c.ctxt.Diag("unsupported shift operator: %v", p)
    		}
    		o1 |= uint32(p.From.Offset) /* includes reg, op, etc */
    		rt := int(p.To.Reg)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/ppc64/asm9.go

    	/* Vector shift */
    	{as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},                 /* vector shift, vx-form */
    	{as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},                /* vector shift algebraic, vx-form */
    	{as: AVSOI, a1: C_U16CON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4}, /* vector shift by octet immediate, va-form */
    
    	/* Vector count */
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 13:55:28 UTC 2024
    - 156.1K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/lite/ir/tfl_ops.td

      );
    }
    
    def TFL_RightShiftOp : TFL_Op<"right_shift", [
        SameOperandsAndResultElementType,
        Pure]> {
      let summary = "Right Shift operator";
    
      let description = [{
        Elementwise computes the bitwise right-shift of `lhs` by `rhs`.
      }];
    
      let arguments = (ins
        TFL_TensorOf<[I8, UI8, I16, UI16, I32, UI32]>:$lhs,
        TFL_TensorOf<[I8, UI8, I16, UI16, I32, UI32]>:$rhs
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jun 06 19:09:08 UTC 2024
    - 186K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tensorflow/transforms/tf_passes.td

        types. Examples of quantized types are TF_Qint8 or TF_Quint8.
    
        An example is TF_DequantizeOp, which converts a quantized type to a float.
        This op is rewritten to generic ops that perform the scale and shift
        and can operate on non-quantized types.
    
        Currently, TF_DequantizeOp is the only op with a lowering that falls
        in this category. When more lowerings are added (e.g. QuantizeV2Op),
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Jun 12 21:18:05 UTC 2024
    - 99.6K bytes
    - Viewed (0)
  7. android/guava/src/com/google/common/cache/LocalCache.java

      /**
       * Mask value for indexing into segments. The upper bits of a key's hash code are used to choose
       * the segment.
       */
      final int segmentMask;
    
      /**
       * Shift value for indexing within segments. Helps prevent entries that end up in the same segment
       * from also ending up in the same bucket.
       */
      final int segmentShift;
    
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Sat May 18 03:24:34 UTC 2024
    - 143.6K bytes
    - Viewed (0)
  8. guava/src/com/google/common/cache/LocalCache.java

      /**
       * Mask value for indexing into segments. The upper bits of a key's hash code are used to choose
       * the segment.
       */
      final int segmentMask;
    
      /**
       * Shift value for indexing within segments. Helps prevent entries that end up in the same segment
       * from also ending up in the same bucket.
       */
      final int segmentShift;
    
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Sat May 18 03:24:34 UTC 2024
    - 149.2K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/x86/asm6.go

    	/* load full pointer - unsupported
    	{AMOVL, Yml, Ycol, movFullPtr, [4]uint8{0, 0, 0, 0}},
    	{AMOVW, Yml, Ycol, movFullPtr, [4]uint8{Pe, 0, 0, 0}},
    	*/
    
    	// double shift
    	{ASHLL, Yi8, Yrl, Yml, movDoubleShift, [4]uint8{0xa4, 0xa5, 0, 0}},
    	{ASHLL, Ycl, Yrl, Yml, movDoubleShift, [4]uint8{0xa4, 0xa5, 0, 0}},
    	{ASHLL, Ycx, Yrl, Yml, movDoubleShift, [4]uint8{0xa4, 0xa5, 0, 0}},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 146.9K bytes
    - Viewed (0)
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