return position - oldPosition;
    }

    ByteBuffer buf = ByteBuffer.wrap(createBuffer());
    long total = 0;
    while (from.read(buf) != -1) {
      Java8Compatibility.flip(buf);
      while (buf.hasRemaining()) {
        total += to.write(buf);
      }
      Java8Compatibility.clear(buf);
    }
    return total;
  }

  /** Max array length on JVM. */

		return errTrailerEOF
	}
	if err != nil {
		return err
	}

	// Make sure there's a header terminator coming up, to prevent
	// a DoS with an unbounded size Trailer. It's not easy to
	// slip in a LimitReader here, as textproto.NewReader requires
	// a concrete *bufio.Reader. Also, we can't get all the way
	// back up to our conn's LimitedReader that *might* be backing

      return position - oldPosition;
    }

    ByteBuffer buf = ByteBuffer.wrap(createBuffer());
    long total = 0;
    while (from.read(buf) != -1) {
      Java8Compatibility.flip(buf);
      while (buf.hasRemaining()) {
        total += to.write(buf);
      }
      Java8Compatibility.clear(buf);
    }
    return total;
  }

  /** Max array length on JVM. */

					79: {CoreID: 39, SocketID: 1, NUMANodeID: 3},
				},
			},
			wantErr: false,
		},
		{

			// FAKE Topology from dual xeon gold 6230
			// (see: dual xeon gold 6230).
			// We flip NUMA cells and Sockets to exercise the code.
			// TODO(fromanirh): replace with a real-world topology
			// once we find a suitable one.
			// Note: this is a fake topology. Thus, there is not a "correct"

			78: {CoreID: 38, SocketID: 1, NUMANodeID: 3},
			79: {CoreID: 39, SocketID: 1, NUMANodeID: 3},
		},
	}
	/*
		FAKE Topology from dual xeon gold 6230
		(see: topoDualSocketMultiNumaPerSocketHT).
		We flip NUMA cells and Sockets to exercise the code.
		TODO(fromanirh): replace with a real-world topology
		once we find a suitable one.
	*/
	fakeTopoMultiSocketDualSocketPerNumaHT = &topology.CPUTopology{
		NumCPUs:      80,

  %0 = "tf.XlaSharding"(%arg0) { _XlaSharding = "\01\02\03"} : (tensor<*xi32>) -> tensor<*xi32>
  %1 = "tf.XlaSharding"(%arg1) { _XlaSharding = "\04\05\06"} : (tensor<*xi32>) -> tensor<*xi32>
  // flip order
  %2 = "tf.A"(%1) : (tensor<*xi32>) -> (tensor<*xi32>)
  %3 = "tf.B"(%0) : (tensor<*xi32>) -> (tensor<*xi32>)
  func.return %2, %3 : tensor<*xi32>, tensor<*xi32>
}

// -----

	VMOVDQU (0*32)(INP), XTMP0
	VMOVDQU (1*32)(INP), XTMP1
	VMOVDQU (2*32)(INP), XTMP2
	VMOVDQU (3*32)(INP), XTMP3

	VMOVDQU flip_mask<>(SB), BYTE_FLIP_MASK

	// Apply Byte Flip Mask: LE -> BE
	VPSHUFB BYTE_FLIP_MASK, XTMP0, XTMP0
	VPSHUFB BYTE_FLIP_MASK, XTMP1, XTMP1
	VPSHUFB BYTE_FLIP_MASK, XTMP2, XTMP2
	VPSHUFB BYTE_FLIP_MASK, XTMP3, XTMP3

	// Transpose data into high/low parts

	MOVL	BX, (g_stack+stack_lo)(BP)
	MOVL	SP, (g_stack+stack_hi)(BP)

	// find out information about the processor we're on
	// first see if CPUID instruction is supported.
	PUSHFL
	PUSHFL
	XORL	$(1<<21), 0(SP) // flip ID bit
	POPFL
	PUSHFL
	POPL	AX
	XORL	0(SP), AX
	POPFL	// restore EFLAGS
	TESTL	$(1<<21), AX
	JNE 	has_cpuid

bad_proc: // show that the program requires MMX.
	MOVL	$2, 0(SP)