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Results 41 - 44 of 44 for relu6 (0.05 sec)

  1. tensorflow/compiler/mlir/tf2xla/tests/legalize-tf-prefer-tf2xla.mlir

        data_format = "NHWC", dilations = [1, 1, 1, 1], epsilon = 9.99999974E-5 : f32, explicit_paddings = [], filter_format = "HWIO", fused_ops = ["BiasAdd", "Relu"], leakyrelu_alpha = 2.000000e-01 : f32, num_args = 2 : i64, operandSegmentSizes = array<i32: 1, 1, 2, 2>, padding = "SAME", strides = [1, 1, 1, 1], use_cudnn_on_gpu = true
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Apr 06 15:32:52 UTC 2024
    - 15.8K bytes
    - Viewed (0)
  2. tensorflow/compiler/mlir/quantization/stablehlo/python/integration_test/quantize_model_test_base.py

          padding: str = 'SAME',
          has_func_alias: bool = False,
      ) -> module.Module:
        class ConvModel(module.Module):
          """A simple model with a single conv2d, bias and relu."""
    
          def __init__(self):
            self.out_channel_size = filter_shape[-1]
    
            # This ensures filters will have different value range per out channel
            self.filters = np.stack(
                [
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue May 14 06:31:57 UTC 2024
    - 18.2K bytes
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  3. tensorflow/compiler/mlir/tfr/python/tfr_gen_test.py

      y = _tfr_quant_raw_data(x)
      s, z = _tfr_quant_qparam(x)
      s = _tfr_quant_scale_factor(1.0, [s, s])
      s = _tfr_quant_scale_factor(1.0, [s])
      y = math_ops.Sub(y, z)
      qmin, qmax = _tfr_quant_act_range('RELU', 1.0, 0)
      (qmin, qmax)  # pylint: disable=pointless-statement
      d = _tfr_quant_rescale(y, s, 0)
      e = math_ops.Cast(x=d, DstT=dtypes.int16)
      f = math_ops.Cast(x=e, DstT=dtypes.int8)
      return f
    
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed Oct 13 16:33:28 UTC 2021
    - 28.8K bytes
    - Viewed (0)
  4. src/cmd/vendor/golang.org/x/arch/x86/x86asm/decode.go

    	xArgRM64         // arg r/m64
    	xArgRM8          // arg r/m8
    	xArgReg          // arg reg
    	xArgRegM16       // arg reg/m16
    	xArgRegM32       // arg reg/m32
    	xArgRegM8        // arg reg/m8
    	xArgRel16        // arg rel16
    	xArgRel32        // arg rel32
    	xArgRel8         // arg rel8
    	xArgSS           // arg SS
    	xArgST           // arg ST, aka ST(0)
    	xArgSTi          // arg ST(i) with +i in opcode
    	xArgSreg         // arg Sreg
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 10 18:59:52 UTC 2023
    - 45.1K bytes
    - Viewed (0)
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