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Results 31 - 40 of 119 for relu (0.04 sec)

  1. tensorflow/compiler/mlir/lite/experimental/tac/tests/get-alternative-subgraph.mlir

        %0 = tfl.add %arg0, %arg1 {fused_activation_function = "RELU6", tac.device = "GPU", tac.inference_type = "FLOAT"} : tensor<1xf32>
        %1 = tfl.mul %0, %arg2 {fused_activation_function = "RELU6", tac.device = "GPU", tac.inference_type = "FLOAT"} : tensor<1xf32>
        func.return %1 : tensor<1xf32>
      }
    
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu May 02 09:41:17 UTC 2024
    - 20.1K bytes
    - Viewed (0)
  2. src/cmd/link/internal/loadelf/ldelf.go

    					symIdx = int(info >> 32)
    				}
    				p = p[8:]
    				if rela != 0 {
    					add = e.Uint64(p)
    					p = p[8:]
    				}
    			} else {
    				// 32-bit rel/rela
    				rOff = int32(e.Uint32(p))
    
    				p = p[4:]
    				info := e.Uint32(p)
    				relocType = uint64(info & 0xff)
    				symIdx = int(info >> 8)
    				p = p[4:]
    				if rela != 0 {
    					add = uint64(e.Uint32(p))
    					p = p[4:]
    				}
    			}
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 16 15:12:12 UTC 2024
    - 33.9K bytes
    - Viewed (0)
  3. platforms/core-configuration/kotlin-dsl/src/integTest/kotlin/org/gradle/kotlin/dsl/compile/BuildScriptCompileAvoidanceIntegrationTest.kt

            configureProject().assertBuildScriptBodyRecompiled().assertOutputContains("bar")
        }
    
        @Test
        @UnsupportedWithConfigurationCache(because = "test rely on configuration phase output")
        fun `avoids buildscript recompilation on included build JAR rebuild`() {
    
            withDefaultSettingsIn("build-logic")
                .appendText("""rootProject.name = "build-logic"""")
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Sun Sep 24 17:45:42 UTC 2023
    - 19.6K bytes
    - Viewed (0)
  4. src/cmd/link/internal/riscv64/asm.go

    	// add to got.plt: pointer to plt[0]
    	gotplt.AddAddrPlus(target.Arch, plt.Sym(), 0)
    
    	// rela
    	rela.AddAddrPlus(target.Arch, gotplt.Sym(), gotplt.Size()-8)
    	sDynid := ldr.SymDynid(s)
    
    	rela.AddUint64(target.Arch, elf.R_INFO(uint32(sDynid), uint32(elf.R_RISCV_JUMP_SLOT)))
    	rela.AddUint64(target.Arch, 0)
    }
    
    func machoreloc1(*sys.Arch, *ld.OutBuf, *loader.Loader, loader.Sym, loader.ExtReloc, int64) bool {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 01 08:06:08 UTC 2024
    - 22.8K bytes
    - Viewed (0)
  5. tensorflow/compiler/mlir/quantization/tensorflow/tests/insert_custom_aggregation_ops.mlir

        %1 = "tf.Relu6"(%0) : (tensor<*xf32>) -> tensor<*xf32>
        func.return %1 : tensor<*xf32>
      }
    }
    
    // CalibrationOptions(calibration_method=CALIBRATION_METHOD_MIN_MAX)
    // MIN-MAX-CHECK: func @wrap_composite_func
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri May 10 04:07:09 UTC 2024
    - 32.1K bytes
    - Viewed (0)
  6. src/cmd/link/internal/arm/asm.go

    	}
    	o(0xe59f0004)
    	o(0xe08f0000)
    
    	o(0xeafffffe)
    	rel, _ := initfunc.AddRel(objabi.R_CALLARM)
    	rel.SetOff(8)
    	rel.SetSiz(4)
    	rel.SetSym(addmoduledata)
    	rel.SetAdd(0xeafffffe) // vomit
    
    	o(0x00000000)
    
    	rel2, _ := initfunc.AddRel(objabi.R_PCREL)
    	rel2.SetOff(12)
    	rel2.SetSiz(4)
    	rel2.SetSym(ctxt.Moduledata)
    	rel2.SetAdd(4)
    }
    
    // Preserve highest 8 bits of a, and do addition to lower 24-bit
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Aug 23 05:58:20 UTC 2023
    - 22.9K bytes
    - Viewed (0)
  7. tensorflow/compiler/mlir/quantization/tensorflow/tests/quantize_xla.mlir

      %biasadd = "tf.BiasAdd"(%conv, %dq_bias) {data_format = "NHWC", device = ""} : (tensor<*xf32>, tensor<2xf32>) -> tensor<*xf32>
      %res = "tf.Relu6"(%biasadd) : (tensor<*xf32>) -> tensor<*xf32>
      %q_res = "quantfork.qcast"(%res) : (tensor<*xf32>) -> tensor<*x!quant.uniform<i8:f32, 0.023529411764705882:-128>>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Wed May 08 19:32:28 UTC 2024
    - 11.4K bytes
    - Viewed (0)
  8. tensorflow/compiler/jit/resource_operation_safety_analysis.cc

    // auto-clustering can only cluster the Read->Write edge, but it is a problem if
    // it clusters the Write->NextIteration->Merge->Read edges instead.  So we rely
    // on auto-clustering to not cluster NextIteration->Merge edges.  The same
    // problem is present for the functional version of the loop above and we also
    // rely on auto-clustering not clustering functional while loops containing
    // resource operations.
    //
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Feb 09 11:36:41 UTC 2024
    - 11.2K bytes
    - Viewed (0)
  9. tensorflow/compiler/mlir/lite/stablehlo/tests/composite-lowering.mlir

      return %2 : tensor<*xf32>
    }
    
    // CHECK-LABEL: gelu_aten
    // CHECK: %0 = "tfl.gelu"(%arg0) <{approximate = false}> : (tensor<5x10xf32>) -> tensor<5x10xf32>
    
    func.func private @gelu_decomp_2(%arg0: tensor<5x10xf32>) -> tensor<5x10xf32>
    func.func @gelu_aten_approximate(%arg0: tensor<5x10xf32>) -> (tensor<*xf32>) {
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Thu Jun 06 18:45:51 UTC 2024
    - 32.6K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/quantization/tensorflow/tests/add_dump_tensor_op.mlir

        %1 = "tf.BiasAdd"(%0, %arg2) {data_format = "NHWC", device = ""} : (tensor<*xf32>, tensor<2xf32>) -> tensor<*xf32>
        %2 = "tf.Relu6"(%1) : (tensor<*xf32>) -> tensor<*xf32>
        func.return %2 : tensor<*xf32>
      }
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Mar 22 22:55:22 UTC 2024
    - 37.9K bytes
    - Viewed (0)
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