// cuDNN prefers NCHW data format for spatial convolutions in f16 before
  // compute capability 7.0 (NVIDIA Tensor Cores).

  // CHECK: "tf.Conv2D"(%[[INPUT_TRANSPOSE:[0-9]*]], %arg1)
  // CHECK-SAME: data_format = "NCHW"
  %0 = "tf.Conv2D"(%input, %filter)
       {
         data_format = "NHWC",
         padding = "VALID",
         strides = [1, 1, 1, 1]

    }

    def "renders only classpath build script configuration"() {
        given:
        project.buildscript.configurations.create("conf1")
        project.buildscript.configurations.create("conf2")

        when:
        task.setRenderer(renderer)
        task.generate()

        then:
        task.reportModel.get().configuration.name == "classpath"
    }

// CHECK: %[[CONV:.+]] = stablehlo.convolution(%[[ARG1]], %[[ARG2]])
// CHECK-SAME: (tensor<1x3x4x3xf32>, tensor<2x3x3x2x!quant.uniform<i8<-127:127>:f32, 0.0023622048182750312>>) -> tensor<1x3x4x2xf32>
// CHECK: return %[[CONV]]

// -----

// Test that per-channel weight-only quantized dot_general op is produced when

 ReadVariableOp 2
 VarHandleOp 435
 _Retval 2
cluster 0 size 2178
 Add 17
 AddN 72
 ArgMax 1
 AssignAddVariableOp 1
 AssignSubVariableOp 106
 BiasAdd 1
 BiasAddGrad 1
 Cast 3
 Const 357
 Conv2D 53
 Conv2DBackpropFilter 53
 Conv2DBackpropInput 52
 DivNoNan 1
 Equal 1
 FusedBatchNorm 53
 FusedBatchNormGrad 53
 Identity 2
 MatMul 3
 MaxPool 1
 MaxPoolGrad 1
 Mean 1
 Mul 164
 Pad 1

// CHECK-NOT: func private @internal_matmul_fn
// CHECK: func private @quantized_matmul_fn
// CHECK-SAME: tf_quant.quantized_ops = ["MatMul"]
// CHECK: func private @quantized_conv2d_fn
// CHECK-SAME: tf_quant.quantized_ops = ["Conv2D"]
// CHECK: func private @quantized_depthwise_conv2d_fn
// CHECK-SAME: tf_quant.quantized_ops = ["DepthwiseConv2D"]

// UQ-CHECK: func private @quantized_conv2d_fn
// UQ-CHECK: func private @quantized_depthwise_conv2d_fn

    func.return %7 : tensor<1x112x112x32x!quant.uniform<u8:f32, 1.0>>

// CHECK: %[[conv:.*]] = "tfl.conv_2d"(%arg0, %arg1, %arg2)
// CHECK-SAME: -> tensor<1x112x112x32x!quant.uniform<u8:f32, 0.0078431372549019607:128>>
// CHECK: %[[cst:.*]] = "tfl.pseudo_qconst"()
// CHECK: %[[add:.*]] = tfl.add(%[[conv]], %[[cst]])
// CHECK-SAME: -> tensor<1x112x112x32x!quant.uniform<u8:f32, 1.000000e+00>>
// CHECK: return %[[add]]
}

 ReadVariableOp 2
 Switch 1
 _Arg 435
 _Retval 2
cluster 0 size 1910
 Add 16
 AddN 71
 ArgMax 1
 AssignAddVariableOp 1
 BiasAdd 1
 BiasAddGrad 1
 Cast 115
 Const 407
 Conv2D 53
 Conv2DBackpropFilter 53
 Conv2DBackpropInput 52
 Equal 1
 FusedBatchNormGradV2 53
 FusedBatchNormV2 53
 MatMul 3
 MaxPool 1
 MaxPoolGrad 1
 Mean 1
 Mul 218
 Pad 2
 ReadVariableOp 538

        def results2 = new Object()

        def store1 = factory.createCachedStore("conf1")
        def store1b = factory.createCachedStore("conf1")
        def store2 = factory.createCachedStore("conf2")

        expect:
        store1.load(() -> results1) == results1
        store1.load(() -> { assert false }) == results1
        store1b.load(() -> { assert false }) == results1

// Verify unused if with functions without side-effects is removed.
// CHECK-LABEL: main
func.func @main(%arg0: tensor<3x15x14x3xf32>) -> tensor<3x15x14x8xf32>
    attributes {tf.entry_function = {inputs = "input", outputs = "Conv2D"}} {
  %cst = arith.constant dense<[0, 1, 2, 3]> : tensor<4xi32>
  %cst_0 = arith.constant dense<1.000000e+00> : tensor<f32>
  %cst_1 = arith.constant dense<0.000000e+00> : tensor<8xf32>

   // Use identity op to avoid the filter being constant-folded.
    %identity = "tf.Identity"(%filter) : (tensor<*xi8>) -> tensor<*xi8>
    %2 = "tf.Cast"(%identity) {Truncate = false} : (tensor<*xi8>) -> tensor<*xf32>
    %3 = "tf.Conv2D"(%input, %2) {
      padding = "VALID", strides = [1, 1, 1, 1],
      attr_map = "strides:0,use_cudnn_on_gpu:1,padding:2,explicit_paddings:3,dilations:4"
    } : (tensor<*xf32>, tensor<*xf32>) -> tensor<*xf32>