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Results 31 - 40 of 74 for conv_2d (0.22 sec)
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tensorflow/compiler/mlir/quantization/tensorflow/tests/fake_quant_e2e_xla.mlir
return %3 : tensor<?x?x?x2xf32> } // CHECK-LABEL: func @conv_with_dynamic_shape // The Conv2D should not be quantized since it has dynamic channel. // CHECK: "tf.Conv2D" // CHECK-SAME: (tensor<?x?x?x?xf32>, tensor<2x3x3x2xf32>) -> tensor<?x?x?x2xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 7.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nchw.mlir
// CHECK: %[[ARG_PERM:.*]] = "tf.Const"() <{value = dense<[0, 3, 1, 2]> : tensor<4xi64>}> // CHECK: %[[ARG_TRANSPOSE:[0-9]*]] = "tf.Transpose"(%arg0, %[[ARG_PERM]]) // CHECK: %[[CONV2D:[0-9]*]] = "tf.Conv2D"(%[[ARG_TRANSPOSE]], %arg1) // CHECK-SAME: data_format = "NCHW" // CHECK-SAME: dilations = [1, 4, 2, 3] // CHECK-SAME: explicit_paddings = [1, 2, 7, 8, 3, 4, 5, 6] // CHECK-SAME: padding = "EXPLICIT"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 9K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_70.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 21 08:41:18 UTC 2022 - 8.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/optimize.mlir
%filter = arith.constant dense<2.0> : tensor<3x3x3x16xf32> %bias = arith.constant dense<3.0> : tensor<16xf32> %value = arith.constant dense<4.0> : tensor<16xf32> %0 = "tf.Conv2D"(%arg, %filter) {T = "tfdtype$DT_FLOAT", data_format = "NHWC", dilations = [1, 2, 3, 1], padding = "SAME", strides = [1, 4, 5, 1]} : (tensor<256x32x32x3xf32>, tensor<3x3x3x16xf32>) -> tensor<256x8x7x16xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Jan 05 18:35:42 UTC 2024 - 3.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir
// CHECK: %[[ARG_PERM:.*]] = "tf.Const"() <{value = dense<[0, 2, 3, 1]> : tensor<4xi64>}> // CHECK: %[[ARG_TRANSPOSE:[0-9]*]] = "tf.Transpose"(%arg0, %[[ARG_PERM]]) // CHECK: %[[CONV2D:[0-9]*]] = "tf.Conv2D"(%[[ARG_TRANSPOSE]], %arg1) // CHECK-SAME: data_format = "NHWC" // CHECK-SAME: dilations = [1, 3, 4, 2] // CHECK-SAME: explicit_paddings = [1, 2, 5, 6, 7, 8, 3, 4] // CHECK-SAME: padding = "EXPLICIT"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 4.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/stablehlo/transforms/fuse_convolution_pass.cc
mul_op.getLoc(), conv_op.getType(), conv_op.getLhs(), new_filter, conv_op.getWindowStridesAttr(), conv_op.getPaddingAttr(), conv_op.getLhsDilationAttr(), conv_op.getRhsDilationAttr(), conv_op.getWindowReversalAttr(), conv_op.getDimensionNumbers(), conv_op.getFeatureGroupCount(), conv_op.getBatchGroupCount(), conv_op.getPrecisionConfigAttr());
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Feb 22 22:21:19 UTC 2024 - 8.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/cast_bf16_ops_to_f32.mlir
%cst = "tf.Const"() {device = "", value = dense_resource<__elided__> : tensor<2x3x3x2xbf16>} : () -> tensor<2x3x3x2xbf16> %0 = "tf.Cast"(%arg0) {Truncate = false, device = ""} : (tensor<1x3x4x3xf32>) -> tensor<1x3x4x3xbf16> %1 = "tf.Conv2D"(%0, %cst) {data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true} : (tensor<1x3x4x3xbf16>, tensor<2x3x3x2xbf16>) -> tensor<1x3x2x2xbf16>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 8.4K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/lift_quantizable_spots_as_functions_xla.mlir
// ----- func.func @conv_with_non_constant_filter(%arg0: tensor<1x3x4x3xf32>, %arg1: tensor<2x3x3x2xf32>) -> tensor<*xf32> { %cst = "tf.Const"() {value = dense<0.000000e+00> : tensor<2xf32>} : () -> tensor<2xf32> %0 = "tf.Conv2D"(%arg0, %arg1) {data_format = "NHWC", dilations = [1, 1, 2, 1], explicit_paddings = [], padding = "SAME", strides = [1, 1, 2, 1], use_cudnn_on_gpu = true} : (tensor<1x3x4x3xf32>, tensor<2x3x3x2xf32>) -> tensor<*xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 8.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/quantization/tensorflow/tests/prepare_quantize_drq_per_channel.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 6.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/mlir2graphdef/fetch_feed_names.mlir
%outputs_2, %control_3 = tf_executor.island(%control_1) wraps "tf.Const"() {value = dense<0.000000e+00> : tensor<5x5x32x16xf32>} : () -> tensor<5x5x32x16xf32> %outputs_4, %control_5 = tf_executor.island wraps "tf.Conv2D"(%outputs, %outputs_2) {data_format = "NHWC", device = "", dilations = [1, 1, 1, 1], explicit_paddings = [], padding = "VALID", strides = [1, 1, 1, 1], use_cudnn_on_gpu = true} : (tensor<*xf32>, tensor<5x5x32x16xf32>) -> tensor<*xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Fri Mar 25 12:28:56 UTC 2022 - 3K bytes - Viewed (0)