#include "mlir/Support/LogicalResult.h"  // from @llvm-project
#include "stablehlo/dialect/StablehloOps.h"  // from @stablehlo

namespace mlir::odml {

namespace {

// Helper class for parsing operands to a foldable operation.
class FoldAdaptor {
 public:
  // Returns std::nullopt if the operation cannot be folded.
  static std::optional<FoldAdaptor> Create(Operation* operation) {

  BFloat16TypePattern(TypeConverter& converter, MLIRContext* ctx)
      : ConversionPattern(converter, MatchAnyOpTypeTag(), /*benefit=*/1, ctx) {}

  LogicalResult matchAndRewrite(
      Operation* op, const ArrayRef<Value> operands,
      ConversionPatternRewriter& rewriter) const override {
    if (getTypeConverter()->isLegal(op)) {
      return failure();
    }
    if (isa<mlir::stablehlo::BitcastConvertOp>(op)) {

    if (!cluster_id) return WalkResult::advance();

    llvm::SmallVector<int, 4> dynamic_shape_arg_index;

    // Traverse the operands of the cluster func op and find which operand
    // is returned by TPUAnnotateTensorsWithDynamicShapeOp.
    for (const auto& cluster_func_operand :
         llvm::enumerate(cluster_func_op.getOperands())) {

// Returns true if a type is quantized tensor type.
bool IsQuantizedTensorType(Type type);

// Returns true if all operands and results are quantized.
bool IsOpFullyQuantized(Operation* op);

// Returns true iff none among operand and result tensors are quantized.
bool IsOpNotQuantized(Operation* op);

}  // namespace quant
}  // namespace mlir

    Example:
      %device_tensor = gpurt.transfer_to_device %cpu_tensor
  }];

  let arguments = (ins TFTensorType);
  let results = (outs TFTensorType);
  let assemblyFormat = "operands attr-dict";
}

// TODO(b/260267885): We may add a device argument when we want to support
// GPU MIG.
def TransferFromDeviceOp: Gpu_Op<"transfer_from_device"> {
  let summary = "Transfer a tensor from device.";

	// 2
	// 4
	// 8
	// 16
}

func ExampleFloat_Cmp() {
	inf := math.Inf(1)
	zero := 0.0

	operands := []float64{-inf, -1.2, -zero, 0, +1.2, +inf}

	fmt.Println("   x     y  cmp")
	fmt.Println("---------------")
	for _, x64 := range operands {
		x := big.NewFloat(x64)
		for _, y64 := range operands {
			y := big.NewFloat(y64)
			fmt.Printf("%4g  %4g  %3d\n", x, y, x.Cmp(y))
		}
		fmt.Println()
	}

// TODO(fengliuai): supports a configurable accumulator bit width.
template <int Bias, int... Operands>
class AccumulatorUniformScale {
 public:
  template <typename ConcreteType>
  class Impl
      : public QuantizationSpecTraitBase<
            ConcreteType, AccumulatorUniformScale<Bias, Operands...>::Impl> {
   public:
    // Whether the index-th operand is a bias.
    static bool IsBias(int index) { return index == Bias; }

 public:
  using TensorflowDataflowAnalysis<
      ResourceConstructingOps>::TensorflowDataflowAnalysis;
  void visitOperation(Operation *op, ArrayRef<const StateT *> operands,
                      ArrayRef<StateT *> results) override {
    if (ForwardThroughTFOperation(op, operands, results)) return;
    setAllToEntryStates(results);
  }
  ~ResourceDataflowAnalysis() override = default;
};

class IsCompositeDataflowAnalysis

  llvm::SmallVector<mlir::Type, 4> operand_types;
  if (options.has_chain) operand_types.push_back(chain_type);
  if (parser.resolveOperands(in_chains, operand_types, loc, result.operands) ||
      parser.resolveOperands(operands, tensor_type, result.operands))
    return mlir::failure();

  if (options.has_chain) result.types.push_back(chain_type);
  result.types.append(num_results, tensor_type);

  } else {
    return {};
  }

  // Fold: Op(Operand, Identity) -> Operand.
  if (rhs_attr && is_valid_broadcasting(lhs_type, rhs_type, result_type)) {
    if (rhs_attr.isSplat() &&
        rhs_attr.getSplatValue<Attribute>() == identity_attr)
      return arithmetic_op.getX();
  }

  // Fold: Op(Identity, Operand) -> Operand for commutative operations.
  if (lhs_attr && is_commutative &&