for i := 1; i <= 15; i++ {
		r := recur(0, int64(i))

		// Print r both as a fraction and as a floating-point number.
		// Since big.Rat implements fmt.Formatter, we can use %-13s to
		// get a left-aligned string representation of the fraction.
		fmt.Printf("%-13s = %s\n", r, r.FloatString(8))
	}

	// Output:
	// 2/1           = 2.00000000
	// 3/1           = 3.00000000
	// 8/3           = 2.66666667

entry:
	ADDV	R4, R14, R12	// R6 start of a, R14 end of a
	BEQ	R4, R12, samebytes // length is 0

	SRLV	$4, R14		// R14 is number of chunks
	BEQ	R0, R14, byte_loop

	// make sure both a and b are aligned.
	OR	R4, R6, R15
	AND	$7, R15
	BNE	R0, R15, byte_loop

	PCALIGN	$16
chunk16_loop:
	BEQ	R0, R14, byte_loop
	MOVV	(R4), R8
	MOVV	(R6), R9
	BNE	R8, R9, byte_loop
	MOVV	8(R4), R16
	MOVV	8(R6), R17

	CMP   R4, $512
	BLT   under512           // special case for < 512
	ANDCC $127, R3, R8       // check for 128 alignment of address
	BEQ   zero512setup

	ANDCC $7, R3, R15
	BEQ   zero512xsetup // at least 8 byte aligned

	// zero bytes up to 8 byte alignment

	ANDCC $1, R3, R15 // check for byte alignment
	BEQ   byte2
	MOVB  R0, 0(R3)   // zero 1 byte
	ADD   $1, R3      // bump ptr by 1
	ADD   $-1, R4

byte2:

    TF_DataType, const int64_t* dims, int num_dims, void* data, size_t len,
    void (*deallocator)(void* data, size_t len, void* arg),
    void* deallocator_arg);

// Returns the alignment, in bytes, required for allocating aligned tensors.
//
// This can be used in combination with TF_NewTensor to manually manage
// memory while ensuring the resulting tensors satisfy TensorFlow's
// memory alignment preferences.

	// Loads or stores smaller than Alignment must be naturally aligned.
	// Loads or stores larger than Alignment need only be Alignment-aligned.
	Alignment int8

	// CanMergeLoads reports whether the backend optimization passes
	// can combine adjacent loads into a single larger, possibly unaligned, load.
	// Note that currently the optimizations must be able to handle little endian byte order.

TEXT ·Or8(SB),NOSPLIT,$0-5
	MOVW	ptr+0(FP), R1
	MOVBU	val+4(FP), R2
	MOVW	$~3, R3	// Align ptr down to 4 bytes so we can use 32-bit load/store.
	AND	R1, R3
#ifdef GOARCH_mips
	// Big endian.  ptr = ptr ^ 3
	XOR	$3, R1
#endif
	AND	$3, R1, R4	// R4 = ((ptr & 3) * 8)
	SLL	$3, R4
	SLL	R4, R2, R2	// Shift val for aligned ptr. R2 = val << R4
	SYNC
try_or8:
	LL	(R3), R4	// R4 = *R3
	OR	R2, R4

 * units away from 0 and 0.499 towards 0. The smallest unit this returns is "µs"; the largest unit
 * it returns is "s". For values in [-499..499] this returns "  0 µs".
 *
 * The returned string attempts to be column-aligned to 6 characters. For negative and large values
 * the returned string may be longer.
 */
fun formatDuration(ns: Long): String {
  val s =
    when {
      ns <= -999_500_000 -> "${(ns - 500_000_000) / 1_000_000_000} s "

	// bitfield types. The order in which bitfields are laid out
	// in memory is implementation defined, so we can't easily
	// know how a bitfield should correspond to a Go type, even if
	// it appears to be aligned correctly.
	bitfieldType := reflect.TypeOf(bitfields{})
	check := func(name string) {
		_, ok := bitfieldType.FieldByName(name)
		if ok {
			fmt.Fprintf(os.Stderr, "found unexpected bitfields field %s\n", name)

// the compiler word, the link editor word, and the TOC save word.
const MinFrameSize = goarch.MinFrameSize

// StackAlign is the required alignment of the SP register.
// The stack must be at least word aligned, but some architectures require more.

	ifanm := &wireFormat{extOff: sizeofIfAnnouncemsghdrNetBSD7, bodyOff: sizeofIfAnnouncemsghdrNetBSD7}
	ifanm.parse = ifanm.parseInterfaceAnnounceMessage
	// NetBSD 6 and above kernels require 64-bit aligned access to
	// routing facilities.
	return 8, map[int]*wireFormat{
		syscall.RTM_ADD:        rtm,
		syscall.RTM_DELETE:     rtm,
		syscall.RTM_CHANGE:     rtm,
		syscall.RTM_GET:        rtm,