Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 10 of 86 for x7 (0.02 sec)

  1. src/cmd/internal/obj/riscv/testdata/testbranch/branch_test.s

    TEXT ·testBGE(SB),NOSPLIT,$0-17
    	MOV	a+0(FP), X5
    	MOV	b+8(FP), X6
    	MOV	$1, X7
    	BGE	X5, X6, b
    	MOV	$0, X7
    b:
    	MOV	X7, r+16(FP)
    	RET
    
    // func testBGEU(a, b int64) (r bool)
    TEXT ·testBGEU(SB),NOSPLIT,$0-17
    	MOV	a+0(FP), X5
    	MOV	b+8(FP), X6
    	MOV	$1, X7
    	BGEU	X5, X6, b
    	MOV	$0, X7
    b:
    	MOV	X7, r+16(FP)
    	RET
    
    // func testBGEZ(a int64) (r bool)
    TEXT ·testBGEZ(SB),NOSPLIT,$0-9
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Feb 28 21:56:43 UTC 2022
    - 2.4K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64.s

    	MULHU	X5, X6, X7				// b3335302
    	MULHSU	X5, X6, X7				// b3235302
    	MULW	X5, X6, X7				// bb035302
    	DIV	X5, X6, X7				// b3435302
    	DIVU	X5, X6, X7				// b3535302
    	REM	X5, X6, X7				// b3635302
    	REMU	X5, X6, X7				// b3735302
    	DIVW	X5, X6, X7				// bb435302
    	DIVUW	X5, X6, X7				// bb535302
    	REMW	X5, X6, X7				// bb635302
    	REMUW	X5, X6, X7				// bb735302
    
    	// 8.2: Load-Reserved/Store-Conditional
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/avx512enc/gfni_avx512f.s

    	VGF2P8MULB X0, X7, K7, X7                          // 62f2450fcff8
    	VGF2P8MULB 15(R8), X7, K7, X7                      // 62d2450fcfb80f000000
    	VGF2P8MULB (BP), X7, K7, X7                        // 62f2450fcf7d00
    	VGF2P8MULB X15, X9, K7, X7                         // 62d2350fcfff
    	VGF2P8MULB X12, X9, K7, X7                         // 62d2350fcffc
    	VGF2P8MULB X0, X9, K7, X7                          // 62f2350fcff8
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 22.6K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/avx512enc/avx512_ifma.s

    	VPMADD52LUQ X3, X7, K1, X7                         // 62f2c509b4fb
    	VPMADD52LUQ 15(R8), X7, K1, X7                     // 62d2c509b4b80f000000
    	VPMADD52LUQ (BP), X7, K1, X7                       // 62f2c509b47d00
    	VPMADD52LUQ X5, X14, K1, X7                        // 62f28d09b4fd
    	VPMADD52LUQ X31, X14, K1, X7                       // 62928d09b4ff
    	VPMADD52LUQ X3, X14, K1, X7                        // 62f28d09b4fb
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 13.2K bytes
    - Viewed (0)
  5. src/crypto/sha512/sha512block_riscv64.s

    //     Maj(x, y, z) = (x AND y) XOR (x AND z) XOR (y AND z)
    #define SHA512T2(a, b, c) \
    	ROR	$28, a, X6; \
    	ROR	$34, a, X7; \
    	XOR	X7, X6; \
    	ROR	$39, a, X8; \
    	XOR	X8, X6; \
    	AND	a, b, X7; \
    	AND	a, c, X8; \
    	XOR	X8, X7; \
    	AND	b, c, X9; \
    	XOR	X9, X7; \
    	ADD	X7, X6
    
    // Calculate T1 and T2, then e = d + T1 and a = T1 + T2.
    // The values for e and a are stored in d and h, ready for rotation.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 9.1K bytes
    - Viewed (0)
  6. src/math/dim_riscv64.s

    TEXT ·archMax(SB),NOSPLIT,$0
    	MOVD	x+0(FP), F0
    	MOVD	y+8(FP), F1
    	FCLASSD	F0, X5
    	FCLASSD	F1, X6
    
    	// +Inf special cases
    	MOV	$PosInf, X7
    	BEQ	X7, X5, isMaxX
    	BEQ	X7, X6, isMaxY
    
    	// NaN special cases
    	MOV	$NaN, X7
    	BEQ	X7, X5, isMaxX
    	BEQ	X7, X6, isMaxY
    
    	// normal case
    	FMAXD	F0, F1, F0
    	MOVD	F0, ret+16(FP)
    	RET
    
    isMaxX: // return x
    	MOVD	F0, ret+16(FP)
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 15 15:48:19 UTC 2021
    - 1.2K bytes
    - Viewed (0)
  7. src/image/jpeg/idct.go

    		x4 := s[1]
    		x5 := s[7]
    		x6 := s[5]
    		x7 := s[3]
    
    		// Stage 1.
    		x8 := w7 * (x4 + x5)
    		x4 = x8 + w1mw7*x4
    		x5 = x8 - w1pw7*x5
    		x8 = w3 * (x6 + x7)
    		x6 = x8 - w3mw5*x6
    		x7 = x8 - w3pw5*x7
    
    		// Stage 2.
    		x8 = x0 + x1
    		x0 -= x1
    		x1 = w6 * (x3 + x2)
    		x2 = x1 - w2pw6*x2
    		x3 = x1 + w2mw6*x3
    		x1 = x4 + x6
    		x4 -= x6
    		x6 = x5 + x7
    		x5 -= x7
    
    		// Stage 3.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 02 23:18:37 UTC 2019
    - 5K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/avx512enc/avx512_vbmi2.s

    	VPSHLDVD X0, X7, K7, X7                            // 62f2450f71f8
    	VPSHLDVD 7(AX), X7, K7, X7                         // 62f2450f71b807000000
    	VPSHLDVD (DI), X7, K7, X7                          // 62f2450f713f
    	VPSHLDVD X15, X9, K7, X7                           // 62d2350f71ff
    	VPSHLDVD X12, X9, K7, X7                           // 62d2350f71fc
    	VPSHLDVD X0, X9, K7, X7                            // 62f2350f71f8
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 97.1K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/avx512enc/avx512_vbmi.s

    	VPMULTISHIFTQB X14, X20, K5, X7                    // 62d2dd0583fe
    	VPMULTISHIFTQB 17(SP)(BP*1), X20, K5, X7           // 62f2dd0583bc2c11000000
    	VPMULTISHIFTQB -7(CX)(DX*8), X20, K5, X7           // 62f2dd0583bcd1f9ffffff
    	VPMULTISHIFTQB X9, X7, K5, X7                      // 62d2c50d83f9
    	VPMULTISHIFTQB X7, X7, K5, X7                      // 62f2c50d83ff
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 28.7K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/avx512enc/avx512_bitalg.s

    	VPOPCNTW (DI), K3, Z16                             // 62e2fd4b5407
    	VPSHUFBITQMB X24, X7, K6, K0                       // 6292450e8fc0
    	VPSHUFBITQMB X7, X7, K6, K0                        // 62f2450e8fc7
    	VPSHUFBITQMB X0, X7, K6, K0                        // 62f2450e8fc0
    	VPSHUFBITQMB (R8), X7, K6, K0                      // 62d2450e8f00
    	VPSHUFBITQMB 15(DX)(BX*2), X7, K6, K0              // 62f2450e8f845a0f000000
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 10.4K bytes
    - Viewed (0)
Back to top