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Results 1 - 3 of 3 for si1 (0.03 sec)

  1. src/cmd/compile/internal/test/switch_test.go

    	benchmarkSwitchInterfaceType(b, false)
    }
    
    type SI0 interface {
    	si0()
    }
    type ST0 struct {
    }
    
    func (ST0) si0() {
    }
    
    type SI1 interface {
    	si1()
    }
    type ST1 struct {
    }
    
    func (ST1) si1() {
    }
    
    type SI2 interface {
    	si2()
    }
    type ST2 struct {
    }
    
    func (ST2) si2() {
    }
    
    type SI3 interface {
    	si3()
    }
    type ST3 struct {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Oct 06 15:42:30 UTC 2023
    - 4.2K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/asm9_gtables.go

    	o1 |= uint32(p.From.Reg&0x1f) << 16                        // RA
    	o0 |= uint32((p.RestArgs[0].Addr.Offset>>16)&0x3ffff) << 0 // si0
    	o1 |= uint32(p.RestArgs[0].Addr.Offset&0xffff) << 0        // si1
    	o0 |= uint32(p.RestArgs[1].Addr.Offset&0x1) << 20          // R
    	out[1] = o1
    	out[0] = o0
    }
    
    // pextd RA,RS,RB
    func type_pextd(c *ctxt9, p *obj.Prog, t *Optab, out *[5]uint32) {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 16 20:18:50 UTC 2022
    - 42.6K bytes
    - Viewed (0)
  3. tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf.cc

    //
    // TF unsorted segment reduction op peforms the following calculation:
    //
    // Assume segment ids' shape is [SI0, SI1, ..., SIm] and data's  shape is
    // [D0, D1, ..., Dn]. Note that segment ids' shape must be a prefix of data's
    // shape, so we can have data's shape represented as [SI0, SI1, ..., SIm,
    // Dm+1, ..., Dn]. Then
    //   output[segment_ids[SI_i0, SI_i1, ..., SI_im], D_im+1, ..., D_in] =
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 11 20:00:43 UTC 2024
    - 291.8K bytes
    - Viewed (0)
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