Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 10 of 2,188 for rulesv4 (0.12 sec)

  1. tools/istio-iptables/pkg/builder/iptables_builder_impl.go

    type Rule struct {
    	chain  string
    	table  string
    	params []string
    }
    
    // Rules represents iptables for V4 and V6
    type Rules struct {
    	rulesv4 []*Rule
    	rulesv6 []*Rule
    }
    
    // IptablesRuleBuilder is an implementation for IptablesRuleBuilder interface
    type IptablesRuleBuilder struct {
    	rules Rules
    	cfg   *config.Config
    }
    
    // NewIptablesBuilders creates a new IptablesRuleBuilder
    Registered: Fri Jun 14 15:00:06 UTC 2024
    - Last Modified: Tue Jun 11 14:29:54 UTC 2024
    - 8.3K bytes
    - Viewed (0)
  2. internal/event/rules.go

    		rulesCopy[pattern] = targetIDSet.Clone()
    	}
    
    	return rulesCopy
    }
    
    // Union - returns union with given rules as new rules.
    func (rules Rules) Union(rules2 Rules) Rules {
    	nrules := rules.Clone()
    
    	for pattern, targetIDSet := range rules2 {
    		nrules[pattern] = nrules[pattern].Union(targetIDSet)
    	}
    
    	return nrules
    }
    
    // Difference - returns difference with given rules as new rules.
    Registered: Sun Jun 16 00:44:34 UTC 2024
    - Last Modified: Fri May 24 23:05:23 UTC 2024
    - 2.7K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/AMD64splitload.rules

    // This file contains rules used by flagalloc and addressingmodes to
    // split a flag-generating merged load op into separate load and op.
    // Unlike with the other rules files, not all of these
    // rules will be applied to all values.
    // Rather, flagalloc will request for rules to be applied
    // to a particular problematic value.
    // These are often the exact inverse of rules in AMD64.rules,
    // only with the conditions removed.
    //
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Oct 04 19:35:46 UTC 2022
    - 3.4K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules

    // Copyright 2022 The Go Authors. All rights reserved.
    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    // This file contains rules used by the laterLower pass.
    // These are often the exact inverse of rules in ARM64.rules.
    
    (ADDconst [c] x) && !isARM64addcon(c)  => (ADD x (MOVDconst [c]))
    (SUBconst [c] x) && !isARM64addcon(c)  => (SUB x (MOVDconst [c]))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 4.1K bytes
    - Viewed (0)
  5. platforms/core-configuration/model-core/src/main/java/org/gradle/model/Rules.java

    import java.lang.annotation.Target;
    
    /**
     * Denotes that the {@link RuleSource} method rule carrying this annotation defines additional rules based on its inputs.
     */
    @Retention(RetentionPolicy.RUNTIME)
    @Target(ElementType.METHOD)
    @Incubating
    public @interface Rules {
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Thu Sep 28 09:51:04 UTC 2023
    - 1K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/386splitload.rules

    // Copyright 2019 The Go Authors. All rights reserved.
    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    // See the top of AMD64splitload.rules for discussion of these rules.
    
    (CMP(L|W|B)load {sym} [off] ptr x mem) => (CMP(L|W|B) (MOV(L|W|B)load {sym} [off] ptr mem) x)
    
    (CMPLconstload {sym} [vo] ptr mem) => (CMPLconst (MOVLload {sym} [vo.Off()] ptr mem) [vo.Val()])
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Oct 04 19:35:46 UTC 2022
    - 620 bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules

    // Copyright 2022 The Go Authors. All rights reserved.
    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    // This file contains rules used by the laterLower pass.
    
    // Simplify ISEL x $0 z into ISELZ
    (ISEL [a] x (MOVDconst [0]) z) => (ISELZ [a] x z)
    // Simplify ISEL $0 y z into ISELZ by inverting comparison and reversing arguments.
    (ISEL [a] (MOVDconst [0]) y z) => (ISELZ [a^0x4] y z)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 3.8K bytes
    - Viewed (0)
  8. platforms/documentation/docs/src/snippets/ant/useExternalAntTaskWithConfig/groovy/pmd-rules.xml

    <?xml version="1.0"?>
    <ruleset name="Custom ruleset"
        xmlns="http://pmd.sf.net/ruleset/1.0.0"
        xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
        xsi:schemaLocation="http://pmd.sf.net/ruleset/1.0.0 http://pmd.sf.net/ruleset_xml_schema.xsd"
        xsi:noNamespaceSchemaLocation="http://pmd.sf.net/ruleset_xml_schema.xsd">
      <description>
      This ruleset checks my code for bad stuff
      </description>
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Mon Nov 27 17:53:42 UTC 2023
    - 419 bytes
    - Viewed (0)
  9. platforms/documentation/docs/src/snippets/ant/useExternalAntTaskWithConfig/kotlin/pmd-rules.xml

    <?xml version="1.0"?>
    <ruleset name="Custom ruleset"
        xmlns="http://pmd.sf.net/ruleset/1.0.0"
        xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
        xsi:schemaLocation="http://pmd.sf.net/ruleset/1.0.0 http://pmd.sf.net/ruleset_xml_schema.xsd"
        xsi:noNamespaceSchemaLocation="http://pmd.sf.net/ruleset_xml_schema.xsd">
      <description>
      This ruleset checks my code for bad stuff
      </description>
    Registered: Wed Jun 12 18:38:38 UTC 2024
    - Last Modified: Mon Nov 27 17:53:42 UTC 2023
    - 419 bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules

    the shift input.
    L6:(SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y)
    L7:(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y)
    L8:(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y)
    L9:
    L10:// See comments in ARM64latelower.rules for why these are here.
    L11:(MOVLQZX x) && zeroUpper32Bits(x,3) => x
    L12:(MOVWQZX x) && zeroUpper48Bits(x,3) => x
    L13:(MOVBQZX x) && zeroUpper56Bits(x,3) => x
    ...
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 636 bytes
    - Viewed (0)
Back to top