rulesCopy[pattern] = targetIDSet.Clone()
	}

	return rulesCopy
}

// Union - returns union with given rules as new rules.
func (rules Rules) Union(rules2 Rules) Rules {
	nrules := rules.Clone()

	for pattern, targetIDSet := range rules2 {
		nrules[pattern] = nrules[pattern].Union(targetIDSet)
	}

	return nrules
}

// Difference - returns difference with given rules as new rules.

		Spec:       flowcontrol.FlowSchemaSpec{}}
	// 5% chance of zero rules, otherwise draw from 1--6 biased low
	nRules := (1 + rng.Intn(3)) * (1 + rng.Intn(2)) * ((19 + rng.Intn(20)) / 20)
	ftr := &fsTestingRecord{fs: fs,
		wellFormed:                    true,
		matchesAllResourceRequests:    nRules > 0 && rng.Float32() < 0.1,
		matchesAllNonResourceRequests: nRules > 0 && rng.Float32() < 0.1,
		digests: map[bool]map[bool][]RequestDigest{

				continue
			}
			return err
		}
		var nRules []sreplication.Rule
		for _, r := range config.Rules {
			if _, ok := m[r.Destination.Bucket]; !ok {
				nRules = append(nRules, r)
			}
		}
		if len(nRules) > 0 {
			config.Rules = nRules
			configData, err := xml.Marshal(config)
			if err != nil {
				return err
			}

// This file contains rules used by flagalloc and addressingmodes to
// split a flag-generating merged load op into separate load and op.
// Unlike with the other rules files, not all of these
// rules will be applied to all values.
// Rather, flagalloc will request for rules to be applied
// to a particular problematic value.
// These are often the exact inverse of rules in AMD64.rules,
// only with the conditions removed.
//

// Copyright 2022 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This file contains rules used by the laterLower pass.
// These are often the exact inverse of rules in ARM64.rules.

(ADDconst [c] x) && !isARM64addcon(c)  => (ADD x (MOVDconst [c]))
(SUBconst [c] x) && !isARM64addcon(c)  => (SUB x (MOVDconst [c]))

import java.lang.annotation.Target;

/**
 * Denotes that the {@link RuleSource} method rule carrying this annotation defines additional rules based on its inputs.
 */
@Retention(RetentionPolicy.RUNTIME)
@Target(ElementType.METHOD)
@Incubating
public @interface Rules {

// Copyright 2019 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// See the top of AMD64splitload.rules for discussion of these rules.

(CMP(L|W|B)load {sym} [off] ptr x mem) => (CMP(L|W|B) (MOV(L|W|B)load {sym} [off] ptr mem) x)

(CMPLconstload {sym} [vo] ptr mem) => (CMPLconst (MOVLload {sym} [vo.Off()] ptr mem) [vo.Val()])

// Copyright 2022 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This file contains rules used by the laterLower pass.

// Simplify ISEL x $0 z into ISELZ
(ISEL [a] x (MOVDconst [0]) z) => (ISELZ [a] x z)
// Simplify ISEL $0 y z into ISELZ by inverting comparison and reversing arguments.
(ISEL [a] (MOVDconst [0]) y z) => (ISELZ [a^0x4] y z)

the shift input.
L6:(SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y)
L7:(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y)
L8:(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y)
L9:
L10:// See comments in ARM64latelower.rules for why these are here.
L11:(MOVLQZX x) && zeroUpper32Bits(x,3) => x
L12:(MOVWQZX x) && zeroUpper48Bits(x,3) => x
L13:(MOVBQZX x) && zeroUpper56Bits(x,3) => x
...

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This file contains rules to decompose builtin compound types
// (complex,string,slice,interface) into their constituent
// types.  These rules work together with the decomposeBuiltIn
// pass which handles phis of these types.

(Store {t} _ _ mem) && t.Size() == 0 => mem

// complex ops