//	}
	NOP	F2

//	LNOP ',' rreg // asm doesn't support the leading comma.
//	{
//		outcode(int($1), &nullgen, 0, &$3);
//	}
	NOP	R2

//	LNOP ',' freg // asm doesn't support the leading comma.
//	{
//		outcode(int($1), &nullgen, 0, &$3);
//	}
	NOP	F2

//	LNOP imm
//	{
//		outcode(int($1), &$2, 0, &nullgen);
//	}
	NOP	$4

//
// special
//
	SYSCALL

	//TODO: FMULP F0, F2                    // deca
	//TODO: FMULP F0, F3                    // decb
	//TODO: FNCLEX                          // dbe2
	//TODO: FNINIT                          // dbe3
	FNOP                                    // d9d0
	//TODO: FNSAVEL (BX)                    // dd33
	//TODO: FNSAVEL (R11)                   // 41dd33
	//TODO: FNSTCW (BX)                     // d93b

	BLT CR6,0(PC)                   // 41980000
	BVC 0(PC)                       // 40830000
	BVS 0(PC)                       // 41830000
	JMP 8(PC)                       // 48000010

	NOP
	NOP R2
	NOP F2
	NOP $4

	CRAND CR0GT, CR0EQ, CR0SO       // 4c620a02
	CRANDN CR0GT, CR0EQ, CR0SO      // 4c620902
	CREQV CR0GT, CR0EQ, CR0SO       // 4c620a42
	CRNAND CR0GT, CR0EQ, CR0SO      // 4c6209c2

	arm.ABEQ,
	arm.ABNE,
	arm.ABCS,
	arm.ABCC,
	arm.ABMI,
	arm.ABPL,
	arm.ABVS,
	arm.ABVC,
	arm.ABHI,
	arm.ABLS,
	arm.ABGE,
	arm.ABLT,
	arm.ABGT,
	arm.ABLE,
	arm.AB,
	obj.ANOP,
}

// ARMConditionCodes handles the special condition code situation for the ARM.
// It returns a boolean to indicate success; failure means cond was unrecognized.

	JCS	2(PC)
	JMP	(SP)
	JCS	2(PC)
//	JMP	(AX*4) // TODO: This line is silently dropped on the floor!
	JCS	2(PC)
	JMP	(AX)(AX*4)
	JCS	2(PC)
	JMP	R13

// LTYPEN spec4	{ outcode($1, &$2); }
	NOP
	NOP	AX
	NOP	foo+4(SB)

// LTYPES spec5	{ outcode($1, &$2); }
	SHLL	CX, R12
	SHLL	CX, foo+4(SB)
	// Old syntax, still accepted:
	SHLL	CX, R11:AX // SHLL CX, AX, R11

// LTYPEM spec6	{ outcode($1, &$2); }

	0x002f 00047 (x.go:4)	CALL	runtime.printnl(SB)
	0x0034 00052 (x.go:4)	CALL	runtime.printunlock(SB)
	0x0039 00057 (x.go:5)	MOVQ	8(SP), BP
	0x003e 00062 (x.go:5)	ADDQ	$16, SP
	0x0042 00066 (x.go:5)	RET
	0x0043 00067 (x.go:5)	NOP
	0x0043 00067 (x.go:3)	PCDATA	$1, $-1
	0x0043 00067 (x.go:3)	PCDATA	$0, $-1
	0x0043 00067 (x.go:3)	CALL	runtime.morestack_noctxt(SB)
	0x0048 00072 (x.go:3)	JMP	0
...
</pre>

<p>

	B	foo(SB)    // JMP foo(SB)
	BEQ	1(PC)
	BEQ	2(PC)
	TBZ	$1, R1, 2(PC)
	TBNZ	$2, R2, 2(PC)
	JMP	foo(SB)
	CALL	foo(SB)

// ADR
	ADR	next, R11     // ADR R11 // 2b000010
next:
	NOP
	ADR -2(PC), R10    // 0a000010
	ADR 2(PC), R16     // 10000010
	ADR -26(PC), R1    // 01000010
	ADR 12(PC), R2     // 02000010
	ADRP -2(PC), R10   // 0a000090
	ADRP 2(PC), R16    // 10000090

		} else if gomips64 == "softfloat" {
			return []string{"-mabi=64", "-msoft-float"}
		}
	case "mips", "mipsle":
		if gomips == "hardfloat" {
			return []string{"-mabi=32", "-mfp32", "-mhard-float", "-mno-odd-spreg"}
		} else if gomips == "softfloat" {
			return []string{"-mabi=32", "-msoft-float"}
		}
	case "loong64":
		return []string{"-mabi=lp64d"}
	}
	return nil
}

	//	}
	NOP	F2

	//	LNOP ',' rreg // asm doesn't support the leading comma.
	//	{
	//		outcode(int($1), &nullgen, 0, &$3);
	//	}
	NOP	R2

	//	LNOP ',' freg // asm doesn't support the leading comma.
	//	{
	//		outcode(int($1), &nullgen, 0, &$3);
	//	}
	NOP	F2

	//	LNOP imm
	//	{
	//		outcode(int($1), &$2, 0, &nullgen);
	//	}
	NOP	$4

	//
	// special

	PMXVI8GER4 VS1, VS2, $1, $2, $3, A1     // 07903012ec811018
	PMXVI8GER4PP VS1, VS2, $1, $2, $3, A1   // 07903012ec811010
	PMXVI8GER4SPP VS1, VS2, $1, $2, $3, A1  // 07903012ec811318
	PNOP                                    // 0700000000000000
	PSTB R1, $1, 12345678(R2)               // 061000bc9822614e
	PSTD R1, $1, 12345678(R2)               // 041000bcf422614e