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Results 1 - 3 of 3 for mergePPC64RLDICLandSRDconst (0.39 sec)

  1. src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules

    // If the RLDICL does not rotate its value, a shifted value can be merged.
    (RLDICL [em] x:(SRDconst [s] a)) && (em&0xFF0000) == 0 => (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a)
    
    // Convert rotated 32 bit masks on 32 bit values into rlwinm. In general, this leaves the upper 32 bits in an undefined state.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 3.8K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewritePPC64latelower.go

    	// cond: (em&0xFF0000) == 0
    	// result: (RLDICL [mergePPC64RLDICLandSRDconst(em, s)] a)
    	for {
    		em := auxIntToInt64(v.AuxInt)
    		x := v_0
    		if x.Op != OpPPC64SRDconst {
    			break
    		}
    		s := auxIntToInt64(x.AuxInt)
    		a := x.Args[0]
    		if !((em & 0xFF0000) == 0) {
    			break
    		}
    		v.reset(OpPPC64RLDICL)
    		v.AuxInt = int64ToAuxInt(mergePPC64RLDICLandSRDconst(em, s))
    		v.AddArg(a)
    		return true
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 16.5K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/rewrite.go

    // operations can be combined. This functions assumes the two opcodes can
    // be merged, and returns an encoded rotate+mask value of the combined RLDICL.
    func mergePPC64RLDICLandSRDconst(encoded, s int64) int64 {
    	mb := s
    	r := 64 - s
    	// A larger mb is a smaller mask.
    	if (encoded>>8)&0xFF < mb {
    		encoded = (encoded &^ 0xFF00) | mb<<8
    	}
    	// The rotate is expected to be 0.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 64.2K bytes
    - Viewed (0)
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