immh := (x >> 19) & (1<<4 - 1)
		immb := (x >> 16) & (1<<3 - 1)
		if immh == 1 {
			return Imm{(immh << 3) + immb - 8, true}
		} else if (immh >> 1) == 1 {
			return Imm{(immh << 3) + immb - 16, true}
		} else if (immh >> 2) == 1 {
			return Imm{(immh << 3) + immb - 32, true}
		} else if (immh >> 3) == 1 {
			return Imm{(immh << 3) + immb - 64, true}
		} else {
			return nil
		}

//       (64-UInt(immh:immb)) when immh = 01xx
//       (128-UInt(immh:immb)) when immh = 1xxx
//
// - arg_immediate_index_Q_imm4__imm4lt20gt_00__imm4_10:
//     the lowest numbered byte element to be extracted, encoded in the "Q:imm4" field.
//     It can have the following values:
//       imm4<2:0> when Q = 0, imm4<3> = 0
//       imm4 when Q = 1, imm4<3> = x
//
// - arg_sysop_AT_SYS_CR_system:

{"Name":"BFM","Bits":"0|0|1|1|0|0|1|1|0|0|immr:6|imms:6|Rn:5|Rd:5","Arch":"32-bit variant","Syntax":"BFM <Wd>, <Wn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases BFI and BFXIL."},
{"Name":"BFM","Bits":"1|0|1|1|0|0|1|1|0|1|immr:6|imms:6|Rn:5|Rd:5","Arch":"64-bit variant","Syntax":"BFM <Xd>, <Xn>, #<immr>, #<imms>","Code":"","Alias":"This instruction is used by the aliases BFI and BFXIL."},

			c.checkindex(p, index2, 15)
			imm5 |= 1
			imm5 |= index1 << 1
			imm4 |= index2
		case ARNG_H:
			c.checkindex(p, index1, 7)
			c.checkindex(p, index2, 7)
			imm5 |= 2
			imm5 |= index1 << 2
			imm4 |= index2 << 1
		case ARNG_S:
			c.checkindex(p, index1, 3)
			c.checkindex(p, index2, 3)
			imm5 |= 4
			imm5 |= index1 << 3
			imm4 |= index2 << 2
		case ARNG_D:

	return (value >> bit) & 1
}

func bfxpreferred_4(sf, opc1, imms, immr uint32) bool {
	if imms < immr {
		return false
	}
	if (imms>>5 == sf) && (imms&0x1f == 0x1f) {
		return false
	}
	if immr == 0 {
		if sf == 0 && (imms == 7 || imms == 15) {
			return false
		}
		if sf == 1 && opc1 == 0 && (imms == 7 ||
			imms == 15 || imms == 31) {
			return false
		}
	}
	return true
}

		case xArgImm8:
			inst.Args[narg] = Imm(imm8)
			narg++

		case xArgImm8u:
			inst.Args[narg] = Imm(uint8(imm8))
			narg++

		case xArgImm16:
			inst.Args[narg] = Imm(int16(imm))
			narg++

		case xArgImm16u:
			inst.Args[narg] = Imm(uint16(imm))
			narg++

		case xArgImm32:
			inst.Args[narg] = Imm(int32(imm))
			narg++

		case xArgImm64:

	// CMN <Wn|WSP>, #<imm>{, <shift>}
	{0xff00001f, 0x3100001f, CMN, instArgs{arg_Wns, arg_IAddSub}, nil},
	// ADDS <Wd>, <Wn|WSP>, #<imm>{, <shift>}
	{0xff000000, 0x31000000, ADDS, instArgs{arg_Wd, arg_Wns, arg_IAddSub}, nil},
	// CMN <Xn|SP>, #<imm>{, <shift>}
	{0xff00001f, 0xb100001f, CMN, instArgs{arg_Xns, arg_IAddSub}, nil},
	// ADDS <Xd>, <Xn|SP>, #<imm>{, <shift>}

	if p.Spadj == 0 && ins.as == AADDI && ins.imm >= -(1<<12) && ins.imm < 1<<12-1 {
		imm0 := ins.imm / 2
		imm1 := ins.imm - imm0

		// ADDI $(imm/2), REG, TO
		// ADDI $(imm-imm/2), TO, TO
		ins.imm = imm0
		insADDI := &instruction{as: AADDI, rd: ins.rd, rs1: ins.rd, imm: imm1}
		return []*instruction{ins, insADDI}
	}

	// LUI $high, TMP

	{0x0f7000f0, 0x007000b0, 4, LDRHT_EQ, 0x1c04, instArgs{arg_R_12, arg_mem_R_pm_imm8_postindex}},                // LDRHT<c> <Rt>, [<Rn>] {,#+/-<imm8>} cond:4|0|0|0|0|U|1|1|1|Rn:4|Rt:4|imm4H:4|1|0|1|1|imm4L:4

			return ImmAlt{uint8(v), uint8(rot)}
		}
		return Imm(v>>rot | v<<(32-rot))

	case arg_endian:
		return Endian((x >> 9) & 1)

	case arg_fbits:
		return Imm((16 << ((x >> 7) & 1)) - ((x&(1<<4-1))<<1 | (x>>5)&1))

	case arg_fp_0:
		return Imm(0)

	case arg_imm24:
		return Imm(x & (1<<24 - 1))

	case arg_imm5:
		return Imm((x >> 7) & (1<<5 - 1))

	case arg_imm5_32: