infFileName     [MAX_PATH]uint16
	drvDescription  [LINE_LEN]uint16
	hardwareID      [1]uint16
}

func (*DrvInfoDetailData) unsafeSizeOf() uint32 {
	if unsafe.Sizeof(uintptr(0)) == 4 {
		// Windows declares this with pshpack1.h
		return uint32(unsafe.Offsetof(DrvInfoDetailData{}.hardwareID) + unsafe.Sizeof(DrvInfoDetailData{}.hardwareID))
	}
	return uint32(unsafe.Sizeof(DrvInfoDetailData{}))
}

  auto* registered_hardwares = GetRegisteredHardwares();
  for (auto& hardware : *registered_hardwares) {
    if (hardware.unique_name == unique_name) {
      llvm::errs() << "Ignoring duplicate hardware. Hardware " << unique_name
                   << " already registered\n";
      hardware.target_hardware_factory = target_hardware_factory;
      return;
    }
  }

//
// RuntimeMetadata: {
//   hardwares: {
//    ["CPU", "GPU"]
//   }
//
//  subgraph_metadata: {
//    [
//      op1:
//       hardware: 0
//       op_costs: [10, -1],
//      op2:
//       hardware: 1
//       op_costs: [20, 5],
//      op3:
//       hardware: 1
//       op_costs: [30, 10],
//      op4:
//       hardware: 0
//       op_costs: [40, -1],
//    ]
//  }
// }

      }
    });
  }

  // Build the flatbuffer.
  std::vector<flatbuffers::Offset<flatbuffers::String>> hardwares;
  for (const auto& kv : *hardware_names) {
    hardwares.push_back(builder->CreateString(kv.first));
  }

  return CreateHardwareMetadata(*builder, builder->CreateVector(hardwares));
}

}  // namespace

std::optional<std::string> ExportRuntimeMetadata(mlir::ModuleOp module) {

  virtual double GetFuncCost(func::FuncOp* func) const;

  // Returns true if 'op' can run on this Hardware.
  virtual bool IsOpSupported(mlir::Operation* op) const;

  // Switching cost between from hardware and this hardware.
  // If both the hardwares are the same, the transfer cost is basically 0.
  virtual double GetHardwareSwitchingCost(const TargetHardware* from,
                                          size_t buffer_size) const = 0;

# Target Aware Conversion (TAC)

Different hardwares have different capabilities and restrictions.

TAC is designed to leverage hardwares' capabilities to:

*   Perform device-specific optimizations (such as unsupported ops lowering,
    layout transformations, etc.)
*   Graph partitioning based on the hardware costs modeling.
*   It supports general import/export where you can hook your own

  absl::Status RunTacPasses(mlir::ModuleOp* module, bool debug_mode = false);

  // Create instances of all registered hardwares.
  std::vector<std::unique_ptr<tac::TargetHardware>> InstantiateBackends();

  std::unique_ptr<TacImporter> importer_;
  std::unique_ptr<TacExporter> exporter_;
  // Owned list of all target hardware backends.
  std::vector<std::unique_ptr<tac::TargetHardware>> backends_;

namespace TFL {
namespace tac {

// Returns true if 'op' is supported to run on 'hardware'.
bool IsSupported(Operation* op, const std::string& hardware);

// Return proper rewriter patterns for different hardwares.
RewritePatternSet GetHardwareRewritePatterns(MLIRContext* context,
                                             const std::string& hardware);

// Convert quantized ops to float, this will essentially insert dequantize &

// A list of filters for TAC users to run ops/functions on ML hardwares. The
// intuition is that, for ops/functions that can be run on ML hardware (e.g.
// EdgeTPU) and TFLite CPU, TAC users give a hint that they're more performant
// to run on TFLite CPU. These filters give the TAC users freedom to specify the
// parts that they want to use other hardware to accelerate.
message TacFilters {

#define TENSORFLOW_COMPILER_MLIR_LITE_EXPERIMENTAL_TAC_HARDWARES_SIMPLE_HARDWARE_H_

#include "tensorflow/compiler/mlir/lite/experimental/tac/hardwares/target_hardware.h"

namespace mlir {
namespace TFL {
namespace tac {

// A simple hardware is an interface makes you add a target backend easily if
// you don't want too much customization.
//
// It allows you to easily specify the ops capabilities (by