C_SACON    // computed address, 16-bit displacement, possibly SP-relative
	C_LACON    // computed address, 32-bit displacement, possibly SP-relative
	C_DACON    // computed address, 64-bit displacement?
	C_SBRA     // short branch
	C_LBRA     // long branch
	C_SAUTO    // short auto
	C_LAUTO    // long auto
	C_ZOREG    // heap address, register-based, displacement == 0

	return (evex.b2&evexRounding)>>1 != 0
}

// SaeEnabled reports whether SAE suffix is permitted.
func (evex evexBits) SaeEnabled() bool {
	return (evex.b2&evexSae)>>0 != 0
}

// DispMultiplier returns displacement multiplier that is calculated
// based on tuple type, EVEX.W and input size.
// If embedded broadcast is used, bcst should be true.
func (evex evexBits) DispMultiplier(bcst bool) int32 {
	if bcst {

	MOVB	$-1, n-8(SP)          // 92fff010
	MOVB	$255, 4096(R4)        // ebff40000152
	MOVB	$-128, -524288(R5)    // eb8050008052
	MOVB	$1, -524289(R6)       // c0a1fff7ffff41aa60009201a000

	// RX (12-bit displacement) and RXY (20-bit displacement) instruction encoding (e.g: ST vs STY)
	MOVW	R1, 4095(R2)(R3)       // 50132fff
	MOVW	R1, 4096(R2)(R3)       // e31320000150
	MOVWZ	R1, 4095(R2)(R3)       // 50132fff

	if cnt == 0 {
		return p
	}

	// Adjust the frame to account for LR.
	off += base.Ctxt.Arch.FixedFrameSize
	reg := int16(s390x.REGSP)

	// If the off cannot fit in a 12-bit unsigned displacement then we
	// need to create a copy of the stack pointer that we can adjust.
	// We also need to do this if we are going to loop.
	if off < 0 || off > 4096-clearLoopCutoff || cnt > clearLoopCutoff {

	// a relative displacement of referenced symbol's GOT entry to the TOC pointer.
	R_ADDRPOWER_GOT

	// R_ADDRPOWER_GOT_PCREL34 is identical to R_ADDRPOWER_GOT, but uses a PC relative
	// sequence to generate a GOT symbol addresses.
	R_ADDRPOWER_GOT_PCREL34

	// R_ADDRPOWER_PCREL relocates two D-form instructions like R_ADDRPOWER, but
	// inserts the displacement from the place being relocated to the address of the

type facility uint8

const (
	// mandatory facilities
	zarch  facility = 1  // z architecture mode is active
	stflef facility = 7  // store-facility-list-extended
	ldisp  facility = 18 // long-displacement
	eimm   facility = 21 // extended-immediate

	// miscellaneous facilities
	dfp    facility = 42 // decimal-floating-point
	etf3eh facility = 30 // extended-translation 3 enhancement

	// cryptography facilities

type facility uint8

const (
	// mandatory facilities
	zarch  facility = 1  // z architecture mode is active
	stflef facility = 7  // store-facility-list-extended
	ldisp  facility = 18 // long-displacement
	eimm   facility = 21 // extended-immediate

	// miscellaneous facilities
	dfp    facility = 42 // decimal-floating-point
	etf3eh facility = 30 // extended-translation 3 enhancement

	// cryptography facilities

	VADDPD (CX)(AX*2), X1, X28  // 6261f508582441
	VADDPD (CX)(AX*2), X29, X28 // 62619500582441
	VADDPD (CX)(AX*2), X29, X10 // 62719500581441
	VADDPD (CX)(AX*2), X10, X28 // 6261ad08582441
	// EVEX: displacement without Disp8.
	VADDPD 15(AX), X29, X0        // 62f1950058800f000000
	VADDPD 15(AX), X1, X28        // 6261f50858a00f000000
	VADDPD 15(AX), X29, X28       // 6261950058a00f000000

				v := uint64(inst.Enc)<<32 | uint64(inst.SuffixEnc)
				return fmt.Sprintf(".quad 0x%x", v)
			}
		}
		buf.WriteString(str)

	default:
		// Prefixed load/stores do not print the displacement register when R==1 (they are PCrel).
		// This also implies RA should be 0.  Likewise, when R==0, printing of R can be omitted.
		if strings.HasPrefix(opName, "pl") || strings.HasPrefix(opName, "pst") {

}

func (c *ctxtz) regoff(a *obj.Addr) int32 {
	return int32(c.vregoff(a))
}

// find if the displacement is within 12 bit.
func isU12(displacement int32) bool {
	return displacement >= 0 && displacement < DISP12
}

// zopload12 returns the RX op with 12 bit displacement for the given load.
func (c *ctxtz) zopload12(a obj.As) (uint32, bool) {
	switch a {
	case AFMOVD:
		return op_LD, true