PredicateMapTy predicate_map;
  TF_ASSERT_OK(ComputePredicates(*root.graph(), &predicate_map));

  EXPECT_EQ(predicate_map[ControlOutputFor(id_false)], "~*cond_ref:0");
  EXPECT_EQ(predicate_map[ControlOutputFor(id_true)], "*cond_ref:0");
}

void CreateSwitchN(const Scope& scope, Input data, Input output_index,
                   int64_t num_outs, OutputList* outputs) {
  if (!scope.ok()) return;

  // CHECK: [[cond_res:%.*]]:2 = tfrt.cond
  // CHECK-SAME: @cond_true @cond_false(%arg0, %arg1) : (!tfrt.chain, !tfrt_fallback.tf_tensor)
  %2 = "tf.If"(%1, %arg0) {else_branch = @cond_false, then_branch = @cond_true, is_stateless = false} : (tensor<i1>, tensor<i32>) -> tensor<i32>
  // Note: returns %out_op_chain.
  // CHECK: tfrt.return [[cond_res]]#0, [[cond_res]]#1 : !tfrt.chain, !tfrt_fallback.tf_tensor
  func.return %2 : tensor<i32>
}

	case A0 <= r && r <= A7:
		return fmt.Sprintf("a%d", int(r-A0))
	default:
		return fmt.Sprintf("Reg(%d)", int(r))
	}
}

// CondReg is a bit or field in the condition register.
type CondReg int8

const (
	_ CondReg = iota
	// Condition Regster bits
	Cond0LT
	Cond0GT
	Cond0EQ
	Cond0SO
	Cond1LT
	Cond1GT
	Cond1EQ
	Cond1SO
	Cond2LT
	Cond2GT
	Cond2EQ

    EXPECT_NE(while_oc_node, nullptr);

    // Check that cond outside compilation has node "identity_cond_fn".
    const FunctionDef *cond_def = fld.Find("oc_cond_host_while_cond_fn");
    EXPECT_NE(cond_def, nullptr);
    bool has_identity_cond_fn_node = false;
    for (const auto &node_def : cond_def->node_def()) {
      if (node_def.name() == "identity_cond_fn") {
        has_identity_cond_fn_node = true;
        break;
      }

	switch a.Type {
	default:
		return nil
	case TypeUnknown:
		return nil
	case TypeReg:
		return R0 + Reg(a.BitFields.Parse(i))
	case TypeCondRegBit:
		return Cond0LT + CondReg(a.BitFields.Parse(i))
	case TypeCondRegField:
		return CR0 + CondReg(a.BitFields.Parse(i))
	case TypeFPReg:
		return F0 + Reg(a.BitFields.Parse(i))
	case TypeVecReg:
		return V0 + Reg(a.BitFields.Parse(i))
	case TypeVecSReg:

		STD, STDU,
		STFD, STFDU,
		STFS, STFSU,
		STQ, HASHST, HASHSTP:
		return op + " " + strings.Join(args, ",")

	case FCMPU, FCMPO, CMPD, CMPDI, CMPLD, CMPLDI, CMPW, CMPWI, CMPLW, CMPLWI:
		crf := int(inst.Args[0].(CondReg) - CR0)
		cmpstr := op + " " + args[1] + "," + args[2]
		if crf != 0 { // print CRx as the final operand if not implied (i.e BF != 0)
			cmpstr += "," + args[0]
		}
		return cmpstr

	case LIS:

		}
	}
	switch arg := arg.(type) {
	case Reg:
		if isLoadStoreOp(inst.Op) && argIndex == 1 && arg == R0 {
			return "0"
		}
		return arg.String()
	case CondReg:
		// The CondReg can either be found in a CMP, where the
		// condition register field is being set, or in an instruction
		// like a branch or isel that is testing a bit in a condition
		// register field.

// CHECK: func @"while_cond_lt9/tf_mlrt_predicate"([[arg:%.*]]: !tf_mlrt.tensor) -> i1
// CHECK: [[cond_res:%.*]] = call @while_cond_lt9([[arg]]) : (!tf_mlrt.tensor) -> !tf_mlrt.tensor
// CHECK: [[bool_res:%.*]] = tf_mlrt.predicate [[cond_res]]
// CHECK: return [[bool_res]] : i1

// CHECK-LABEL: func @multi_while_test
func.func @multi_while_test() -> (tensor<i32>, tensor<i32>) {