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src/cmd/asm/internal/asm/testdata/armerror.s
NMULSF F0, F1 // ERROR "illegal combination" FMULAD F0, F1 // ERROR "illegal combination" FMULAF F0, F1 // ERROR "illegal combination" FMULSD F0, F1 // ERROR "illegal combination" FMULSF F0, F1 // ERROR "illegal combination" FNMULAD F0, F1 // ERROR "illegal combination" FNMULAF F0, F1 // ERROR "illegal combination"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Nov 03 14:06:21 GMT 2017 - 14.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 37.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
// Copyright 2015 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This contains the majority of valid opcode combinations // available in cmd/internal/obj/ppc64/asm9.go with // their valid instruction encodings. #include "../../../../../runtime/textflag.h" // In case of index mode instructions, usage of // (Rx)(R0) is equivalent to (Rx+R0)
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Apr 24 15:53:25 GMT 2024 - 49K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// } SLL $4, R1, R2 // LSHW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SLL $4, R1 // // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1 MOVW $1, R1 // LMOVW ximm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // }
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64_p10.s
// Copyright 2022 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This contains the valid opcode combinations available // in cmd/internal/obj/ppc64/asm9.go which exist for // POWER10/ISA 3.1. #include "../../../../../runtime/textflag.h" TEXT asmtest(SB), DUPOK|NOSPLIT, $0 BRD R1, R2 // 7c220176
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Thu Mar 23 20:52:57 GMT 2023 - 14.3K bytes - Viewed (0) -
operator/cmd/mesh/testdata/manifest-generate/data-snapshot.tar.gz
new settings and versions can be performed by a different role than the prod version. The intended users of this repo are users running Istio in production who want to select, tune and understand each binary that gets deployed, and select which combination to use. Note: each component can be installed in parallel with an existing Istio 1.0 or 1.1 installation in `istio-system`. The new components will not interfere with existing apps, but can interoperate, and it is possible to gradually move apps...
Others - Registered: Wed May 08 22:53:08 GMT 2024 - Last Modified: Wed Jan 10 05:10:03 GMT 2024 - 198.1K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/mips64.s
// { // outcode(int($1), &$2, 0, &$4); // } AND $11, R17, R7 // 3227000b XOR $341, R1, R23 // 38370155 OR $254, R25, R13 // 372d00fe // // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1 MOVV $1, R1 // LMOVW ximm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
// This input extends auto-generated amd64enc.s test suite // with manually added tests. #include "../../../../../runtime/textflag.h" TEXT asmtest(SB),DUPOK|NOSPLIT,$0 // AVX2GATHER: basic combinations. VPGATHERDQ Y2, (BP)(X7*2), Y1 // c4e2ed904c7d00 VPGATHERDQ X12, (R13)(X14*2), X11 // c40299905c7500 VPGATHERDQ Y12, (R13)(X14*2), Y11 // c4029d905c7500
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0)