ch2[myChan]()

	// P can be inferred as there's a single specific type and no tilde.
	var e int
	ch3(e)

	// P cannot be inferred as there's more than one specific type and a tilde.
	ch4 /* ERROR "cannot infer P" */ (e)
	_ = ch4[chan int]

	// P cannot be inferred as there's more than one specific type.
	ch5 /* ERROR "cannot infer P" */ ()
	ch5[chan<- int]()
}

// test case from issue

         "tf.TestAsyncTfrtAsyncThread"() {T = i32} num_args(1)
  %ch3 = tfrt_fallback_async.createop(%ch2) key(2) device("/CPU:0")
         "tf.TestPrintThreadName"() num_args(0)

  %ch4, %0 = tfrt_fallback_async.executeop.seq(%ch3) key(0) cost(100)
             device("/CPU:0") "tf.Const"()
             { dtype = i32, value = dense<[2]> : tensor<1xi32> } : 1

	}(G2(672.5), int32(35)) < m3[<-m5[func(int64, int64) G1 {
		return i8_1
	}(*pi64_0, int64(50))]][15&i1^i2^i2].m0[G2(895.3)] || (func(int64, uint) uint {
		return uint(94)
	}(int64(30), uint(95))&^<-ch2^<-ch4)&<-ch2^<-ch4 == <-ch2 {
		var f0 float64
		var pf2 *float64
		var ch5, ch6 chan int16
		var fnc0 func(*int64, G2, struct {
			i8_0  G1
			m1    map[float64]bool
			i64_2 int64

  %s = "tfrt_test.get_string"() { value = "Running @matmul_cpu" } : () -> !tfrt.string
  %ch4 = "tfrt_test.print_string"(%s, %ch3) : (!tfrt.string, !tfrt.chain) -> (!tfrt.chain)

  %ch5 = "tfrt_fallback_async.print_tensor"(%result, %ch4) : (!tfrt_fallback.tf_tensor, !tfrt.chain) -> !tfrt.chain

  tfrt.return %ch5, %result : !tfrt.chain, !tfrt_fallback.tf_tensor
}

	ch chan int
	rc <-chan float64
	sc chan <- string
	ch0 = +ch /* ERROR "not defined" */
	ch1 = -ch /* ERROR "not defined" */
	ch2 = !ch /* ERROR "not defined" */
	ch3 = ^ch /* ERROR "not defined" */
	ch4 = *ch /* ERROR "cannot indirect" */
	ch5 = &ch
	ch6 = *ch5
	ch7 = <-ch
	ch8 = <-rc
	ch9 = <-sc /* ERROR "cannot receive" */
	ch10, ok = <-ch
	// ok is of type bool
	ch11, myok = <-ch

 * $FreeBSD: src/sys/powerpc/include/elf.h,v 1.7 2004/11/02 09:47:01 ssouhlal Exp $
 * $FreeBSD: src/sys/sparc64/include/elf.h,v 1.12 2003/09/25 01:10:26 peter Exp $
 * "System V ABI" (http://www.sco.com/developers/gabi/latest/ch4.eheader.html)
 * "ELF for the ARM® 64-bit Architecture (AArch64)" (ARM IHI 0056B)
 * "RISC-V ELF psABI specification" (https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc)