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Results 1 - 10 of 39 for bic (0.03 sec)
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src/cmd/asm/internal/asm/testdata/arm.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/runtime/sys_openbsd_arm.s
MOVW R13, R9 SUB $8, R13 BIC $0x7, R13 // align for ELF ABI MOVW 4(R0), R1 // arg 2 - flags MOVW 8(R0), R2 // arg 3 - mode (vararg, on stack) MOVW R2, 0(R13) MOVW 0(R0), R0 // arg 1 - path MOVW R13, R4 BIC $0x7, R13 // align for ELF ABI BL libc_open(SB) MOVW R9, R13 RET TEXT runtime·close_trampoline(SB),NOSPLIT,$0 MOVW R13, R9 BIC $0x7, R13 // align for ELF ABI
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 18.5K bytes - Viewed (0) -
src/cmd/dist/vfp_arm.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 651 bytes - Viewed (0) -
test/codegen/bits.go
// arm64:`AND\t` return a & (1 << 63) } func and_mask_3(a, b uint32) (uint32, uint32) { // arm/7:`BIC`,-`AND` a &= 0xffffaaaa // arm/7:`BFC`,-`AND`,-`BIC` b &= 0xffc003ff return a, b } // Check generation of arm64 BIC/EON/ORN instructions func op_bic(x, y uint32) uint32 { // arm64:`BIC\t`,-`AND` return x &^ y } func op_eon(x, y, z uint32, a []uint32, n, m uint64) uint64 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 7.8K bytes - Viewed (0) -
src/internal/bytealg/equal_arm64.s
// R2: data len // at return: result in R0 TEXT memeqbody<>(SB),NOSPLIT,$0 CMP $1, R2 // handle 1-byte special case for better performance BEQ one CMP $16, R2 // handle specially if length < 16 BLO tail BIC $0x3f, R2, R3 CBZ R3, chunk16 // work with 64-byte chunks ADD R3, R0, R6 // end of chunks chunk64_loop: VLD1.P (R0), [V0.D2, V1.D2, V2.D2, V3.D2] VLD1.P (R1), [V4.D2, V5.D2, V6.D2, V7.D2] VCMEQ V0.D2, V4.D2, V8.D2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jan 24 16:07:25 UTC 2024 - 2.5K bytes - Viewed (0) -
src/internal/bytealg/count_arm64.s
BLO tail ANDS $0x1f, R0, R9 BEQ chunk // Work with not 32-byte aligned head BIC $0x1f, R0, R3 ADD $0x20, R3 PCALIGN $16 head_loop: MOVBU.P 1(R0), R5 CMP R5, R1 CINC EQ, R11, R11 SUB $1, R2, R2 CMP R0, R3 BNE head_loop // Work with 32-byte aligned chunks chunk: BIC $0x1f, R2, R9 // The first chunk can also be the last CBZ R9, tail // R3 = end of 32-byte chunks
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Oct 31 17:00:27 UTC 2023 - 2K bytes - Viewed (0) -
src/runtime/sys_windows_arm.s
MOVW 8(R4), R12 // libcall->args // Do we have more than 4 arguments? MOVW 4(R4), R0 // libcall->n SUB.S $4, R0, R2 BLE loadregs // Reserve stack space for remaining args SUB R2<<2, R13 BIC $0x7, R13 // alignment for ABI // R0: count of arguments // R1: // R2: loop counter, from 0 to (n-4) // R3: scratch // R4: pointer to libcall struct // R12: libcall->args MOVW $0, R2 stackargs:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 21 15:56:43 UTC 2023 - 7.7K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
package arm import "cmd/internal/obj" var Anames = []string{ obj.A_ARCHSPECIFIC: "AND", "EOR", "SUB", "RSB", "ADD", "ADC", "SBC", "RSC", "TST", "TEQ", "CMP", "CMN", "ORR", "BIC", "MVN", "BEQ", "BNE", "BCS", "BHS", "BCC", "BLO", "BMI", "BPL", "BVS", "BVC", "BHI", "BLS", "BGE", "BLT", "BGT", "BLE", "MOVWD", "MOVWF", "MOVDW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/flags_arm64_test.s
CMP R1, R0 WORD $0xd53b4200 // MOVD NZCV, R0 MOVD R0, ret+16(FP) RET TEXT ·asmAndFlags(SB),NOSPLIT,$0-24 MOVD x+0(FP), R0 MOVD y+8(FP), R1 TST R1, R0 WORD $0xd53b4200 // MOVD NZCV, R0 BIC $0x30000000, R0 // clear C, V bits, as TST does not change those flags MOVD R0, ret+16(FP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 13 09:12:17 UTC 2021 - 699 bytes - Viewed (0) -
src/runtime/tls_arm.s
// To make stack unwinding work, this function should NOT be marked as NOFRAME, // as it may contain a call, which clobbers LR even just temporarily. MRC 15, 0, R0, C13, C0, 3 // fetch TLS base pointer BIC $3, R0 // Darwin/ARM might return unaligned pointer MOVW runtime·tls_g(SB), R11 ADD R11, R0 MOVW g, 0(R0) MOVW g, R0 // preserve R0 across call to setg<> RET // load_g loads the g register from pthread-provided
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 10 20:38:07 UTC 2022 - 3.5K bytes - Viewed (0)