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test/codegen/comparisons.go
// amd64:`CMPW\tcommand-line-arguments[.+_a-z0-9]+\(SP\), [A-Z]` return a == b } func CompareArray4(a, b [12]int8) bool { // amd64:`CMPQ\tcommand-line-arguments[.+_a-z0-9]+\(SP\), [A-Z]` // amd64:`CMPL\tcommand-line-arguments[.+_a-z0-9]+\(SP\), [A-Z]` return a == b } func CompareArray5(a, b [15]byte) bool { // amd64:`CMPQ\tcommand-line-arguments[.+_a-z0-9]+\(SP\), [A-Z]`
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 19 16:31:02 UTC 2024 - 15.2K bytes - Viewed (0) -
platforms/native/language-native/src/test/groovy/org/gradle/language/nativeplatform/internal/incremental/sourceparser/RegexBackedCSourceParserTest.groovy
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Thu Nov 16 20:20:03 UTC 2023 - 34.3K bytes - Viewed (0) -
okcurl/README.md
Registered: Sun Jun 16 04:42:17 UTC 2024 - Last Modified: Sat Jul 09 21:19:04 UTC 2016 - 178 bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/annotate-parameter-replication.mlir
module attributes {tf.versions = {producer = 888 : i32}} { // CHECK-LABEL: func @annotate_broadcast_values func.func @annotate_broadcast_values(%arg0: tensor<?xi32>) -> tensor<?xi32> { %0 = "tf._A"(%arg0) : (tensor<?xi32>) -> tensor<?xi32> %1 = "tf._B"(%arg0) : (tensor<?xi32>) -> tensor<?xi32> %5:2 = tf_device.replicate([%0, %arg0] as %ri_0: tensor<?xi32>) {n = 2 : i32} {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jul 25 02:54:34 UTC 2023 - 4.1K bytes - Viewed (0) -
build-logic-commons/code-quality-rules/src/main/resources/codenarc/codenarc.xml
<property name='staticFinalRegex' value='^logger$|^[A-Z][A-Z_0-9]*$|^serialVersionUID$'/> </rule-config> <rule-config name='MethodName'> <property name='regex' value='^[a-z][\$_a-zA-Z0-9]*$|^.*\s.*$'/> </rule-config> <rule-config name='VariableName'> <property name='finalRegex' value='^[a-z][a-zA-Z0-9]*$'/> </rule-config> <exclude name="ConfusingMethodName"/>
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Wed Dec 09 08:14:05 UTC 2020 - 2.2K bytes - Viewed (0) -
build-logic-commons/code-quality-rules/src/main/resources/codenarc/codenarc-integtests.xml
<property name='staticFinalRegex' value='^logger$|^[A-Z][A-Z_0-9]*$|^serialVersionUID$'/> </rule-config> <rule-config name='MethodName'> <property name='regex' value='^[a-z][\$_a-zA-Z0-9]*$|^.*\s.*$'/> </rule-config> <rule-config name='VariableName'> <property name='finalRegex' value='^[a-z][a-zA-Z0-9]*$'/> </rule-config> <exclude name="ConfusingMethodName"/>
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Wed Dec 09 08:14:05 UTC 2020 - 2.3K bytes - Viewed (0) -
staging/src/k8s.io/apimachinery/pkg/util/validation/validation_test.go
t.Errorf("expected false for '%s'", val) } } } func TestIsCIdentifier(t *testing.T) { goodValues := []string{ "a", "ab", "abc", "a1", "_a", "a_", "a_b", "a_1", "a__1__2__b", "__abc_123", "A", "AB", "AbC", "A1", "_A", "A_", "A_B", "A_1", "A__1__2__B", "__123_ABC", } for _, val := range goodValues { if msgs := IsCIdentifier(val); len(msgs) != 0 { t.Errorf("expected true for '%s': %v", val, msgs)
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Tue Mar 05 04:51:54 UTC 2024 - 22.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nhwc.mlir
-> (tensor<?x256x56x56xf32>, tensor<256xf32>, tensor<256xf32>, tensor<256xf32>, tensor<256xf32>, tensor<*xf32>) // CHECK: %[[BATCH_NORM1:[_a-z0-9]*]], {{.*}} = "tf.FusedBatchNormV3" // CHECK-SAME: %[[CONV1]] // CHECK-SAME: data_format = "NHWC" // ------------------------------------------------------------------------ // // Convolution layer #2.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 7.3K bytes - Viewed (0) -
pkg/apis/policy/validation/validation_test.go
Registered: Sat Jun 15 01:39:40 UTC 2024 - Last Modified: Mon Aug 07 20:44:13 UTC 2023 - 9.1K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/asmz.go
} else if int64(int32(v)) == v { zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm) } else if int64(uint32(v)) == v { zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) } else if uint64(v)&0xffffffff00000000 == uint64(v) { zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm) } else { zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm) zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 16 17:46:09 UTC 2024 - 176.7K bytes - Viewed (0)