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Results 1 - 6 of 6 for XORLconst (0.33 sec)

  1. src/cmd/compile/internal/ssa/_gen/AMD64.rules

    // Fold boolean negation into SETcc.
    (XORLconst [1] (SETNE x)) => (SETEQ x)
    (XORLconst [1] (SETEQ x)) => (SETNE x)
    (XORLconst [1] (SETL  x)) => (SETGE x)
    (XORLconst [1] (SETGE x)) => (SETL  x)
    (XORLconst [1] (SETLE x)) => (SETG  x)
    (XORLconst [1] (SETG  x)) => (SETLE x)
    (XORLconst [1] (SETB  x)) => (SETAE x)
    (XORLconst [1] (SETAE x)) => (SETB  x)
    (XORLconst [1] (SETBE x)) => (SETA  x)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewrite386.go

    	v_0 := v.Args[0]
    	// match: (XORLconst [c] (XORLconst [d] x))
    	// result: (XORLconst [c ^ d] x)
    	for {
    		c := auxIntToInt32(v.AuxInt)
    		if v_0.Op != Op386XORLconst {
    			break
    		}
    		d := auxIntToInt32(v_0.AuxInt)
    		x := v_0.Args[0]
    		v.reset(Op386XORLconst)
    		v.AuxInt = int32ToAuxInt(c ^ d)
    		v.AddArg(x)
    		return true
    	}
    	// match: (XORLconst [c] x)
    	// cond: c==0
    	// result: x
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 21:05:46 UTC 2023
    - 262.4K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/rewriteAMD64.go

    			break
    		}
    		x := v_0.Args[0]
    		v.reset(OpAMD64SETBE)
    		v.AddArg(x)
    		return true
    	}
    	// match: (XORLconst [c] (XORLconst [d] x))
    	// result: (XORLconst [c ^ d] x)
    	for {
    		c := auxIntToInt32(v.AuxInt)
    		if v_0.Op != OpAMD64XORLconst {
    			break
    		}
    		d := auxIntToInt32(v_0.AuxInt)
    		x := v_0.Args[0]
    		v.reset(OpAMD64XORLconst)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 712.7K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/386Ops.go

    		{name: "XORL", argLength: 2, reg: gp21, asm: "XORL", commutative: true, resultInArg0: true, clobberFlags: true}, // arg0 ^ arg1
    		{name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true}, // arg0 ^ auxint
    
    		{name: "CMPL", argLength: 2, reg: gp2flags, asm: "CMPL", typ: "Flags"},                    // arg0 compare to arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 14 08:10:32 UTC 2023
    - 45.1K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/AMD64Ops.go

    		{name: "XORQconst", argLength: 1, reg: gp11, asm: "XORQ", aux: "Int32", resultInArg0: true, clobberFlags: true},                                                 // arg0 ^ auxint
    		{name: "XORLconst", argLength: 1, reg: gp11, asm: "XORL", aux: "Int32", resultInArg0: true, clobberFlags: true},                                                 // arg0 ^ auxint
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Aug 04 16:40:24 UTC 2023
    - 98K bytes
    - Viewed (1)
  6. src/cmd/compile/internal/ssa/opGen.go

    				{0, 239}, // AX CX DX BX BP SI DI
    				{1, 239}, // AX CX DX BX BP SI DI
    			},
    			outputs: []outputInfo{
    				{0, 239}, // AX CX DX BX BP SI DI
    			},
    		},
    	},
    	{
    		name:         "XORLconst",
    		auxType:      auxInt32,
    		argLen:       1,
    		resultInArg0: true,
    		clobberFlags: true,
    		asm:          x86.AXORL,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 239}, // AX CX DX BX BP SI DI
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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