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src/cmd/asm/internal/asm/parse.go
// For ARM, only R0 through R15 may appear. // For ARM64, V0 through V31 with arrangement may appear. // // For 386/AMD64 register list specifies 4VNNIW-style multi-source operand. // For range of 4 elements, Intel manual uses "+3" notation, for example: // // VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128 // // Given asm line: // // VP4DPWSSDS Z5, [Z10-Z13], (AX) //
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