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Results 1 - 2 of 2 for SET (0.23 sec)
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src/cmd/asm/internal/asm/testdata/arm.s
// (($7 & 15) << 12) | /* arm register */ // (($9 & 15) << 16) | /* Crn */ // (($11 & 15) << 0) | /* Crm */ // (($12 & 7) << 5) | /* coprocessor information */ // (1<<4)); /* must be set */ // outcode(AMRC, Always, &nullgen, 0, &g); // } MRC.S 4, 6, R1, C2, C3, 7 // MRC $8301712627 MCR.S 4, 6, R1, C2, C3, 7 // MRC $8300664051 // // MULL r1,r2,(hi,lo) //
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
BGTZ X5, 2(PC) // 63445000 BLE X5, X6, 2(PC) // 63545300 BLEU X5, X6, 2(PC) // 63745300 BLEZ X5, 2(PC) // 63545000 BLTZ X5, 2(PC) // 63c40200 BNEZ X5, 2(PC) // 63940200 // Set pseudo-instructions SEQZ X15, X15 // 93b71700 SNEZ X15, X15 // b337f000 // F extension FABSS F0, F1 // d3200020 FNEGS F0, F1 // d3100020 FNES F0, F1, X7 // d3a300a093c31300
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 22 04:42:21 GMT 2024 - 16.7K bytes - Viewed (1)