(SUBS (SLL y z) x) => (RSBSshiftLLreg x y z)
(SUBS x (SRL y z)) => (SUBSshiftRLreg x y z)
(SUBS (SRL y z) x) => (RSBSshiftRLreg x y z)
(SUBS x (SRA y z)) => (SUBSshiftRAreg x y z)
(SUBS (SRA y z) x) => (RSBSshiftRAreg x y z)
(RSB x (SLLconst [c] y)) => (RSBshiftLL x y [c])
(RSB (SLLconst [c] y) x) => (SUBshiftLL x y [c])
(RSB x (SRLconst [c] y)) => (RSBshiftRL x y [c])
(RSB (SRLconst [c] y) x) => (SUBshiftRL x y [c])

		{name: "RSBSshiftRLreg", argLength: 3, reg: gp31carry, asm: "RSB"}, // arg1>>arg2 - arg0, unsigned shift, set carry flag
		{name: "RSBSshiftRAreg", argLength: 3, reg: gp31carry, asm: "RSB"}, // arg1>>arg2 - arg0, signed shift, set carry flag

		// comparisons

		return true
	}
	return false
}
func rewriteValueARM_OpARMRSBSshiftRAreg(v *Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (RSBSshiftRAreg (MOVWconst [c]) x y)
	// result: (SUBSconst [c] (SRA <x.Type> x y))
	for {
		if v_0.Op != OpARMMOVWconst {
			break
		}
		c := auxIntToInt32(v_0.AuxInt)
		x := v_1
		y := v_2

			},
			outputs: []outputInfo{
				{1, 0},
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "RSBSshiftRAreg",
		argLen: 3,
		asm:    arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14