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Results 1 - 6 of 6 for Orr (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/arm.s

    	ORR	R0->28, R1           // 401e81e1
    	ORR	R0@>28, R1           // 601e81e1
    	ORR.S	R0<<28, R1           // 001e91e1
    	ORR.S	R0>>28, R1           // 201e91e1
    	ORR.S	R0->28, R1           // 401e91e1
    	ORR.S	R0@>28, R1           // 601e91e1
    	ORR	R0<<R1, R2, R3       // 103182e1
    	ORR	R0>>R1, R2, R3       // 303182e1
    	ORR	R0->R1, R2, R3       // 503182e1
    	ORR	R0@>R1, R2, R3       // 703182e1
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/armerror.s

    	XTAH	R0<<16, R5, R2     // ERROR "illegal shift"
    	XTABU	R0->24, R5, R2     // ERROR "illegal shift"
    	XTAHU	R0@>1, R5, R2      // ERROR "illegal shift"
    	AND.W	R0, R1             // ERROR "invalid .W suffix"
    	ORR.P	R2, R3, R4         // ERROR "invalid .P suffix"
    	CMP.S	R1, R2	           // ERROR "invalid .S suffix"
    	BIC.P	$124, R1, R2       // ERROR "invalid .P suffix"
    	MOVW.S	$124, R1           // ERROR "invalid .S suffix"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Oct 23 15:18:14 UTC 2024
    - 14.5K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm64.s

    	AND	$(1<<63-1), R1                      // AND	$9223372036854775807, R1        // 21f84092
    	ORR	$(1<<63), R1                        // ORR	$-9223372036854775808, R1       // 210041b2
    	ORR	$(1<<63-1), R1                      // ORR	$9223372036854775807, R1        // 21f840b2
    	EOR	$(1<<63), R1                        // EOR	$-9223372036854775808, R1       // 210041d2
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 95.3K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	ORNW R4@>11, R16, R3                       // 032ee42a
    	ORN R22@>19, R3, R3                        // 634cf6aa
    	ORRW $4294443071, R15, R24                 // f8490d32
    	ORR $-3458764513820540929, R12, R22        // 96f542b2
    	ORRW R13<<4, R8, R26                       // 1a110d2a
    	ORR R3<<22, R5, R6                         // a65803aa
    	PRFM (R8), $25                             // 190180f9
    	PRFM (R2), PLDL1KEEP                       // 400080f9
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/parse.go

    	case lex.LSH:
    		op = 0
    	case lex.RSH:
    		op = 1
    	case lex.ARR:
    		op = 2
    	case lex.ROT:
    		// following instructions on ARM64 support rotate right
    		// AND, ANDS, TST, BIC, BICS, EON, EOR, ORR, MVN, ORN
    		op = 3
    	}
    	tok := p.next()
    	str := tok.String()
    	var count int16
    	switch tok.ScanToken {
    	case scanner.Ident:
    		if p.arch.Family == sys.ARM64 {
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
    - 37.3K bytes
    - Viewed (0)
  6. lib/fips140/v1.0.0.zip

    CALL p256MulInternal<>(SB) // z1^3 LDx(y2in) CALL p256MulInternal<>(SB) // s2 = z1ˆ3*y2 LDx(s1) CALL p256SubInternal<>(SB) // r = s2 - s1 STx(r) MOVD $1, t2 ORR x0, x1, t0 // Check if zero mod p256 ORR x2, x3, t1 ORR t1, t0, t0 CMP $0, t0 CSEL EQ, t2, ZR, hlp1 EOR $-1, x0, t0 EOR const0, x1, t1 EOR const1, x3, t3 ORR t0, t1, t0 ORR x2, t3, t1 ORR t1, t0, t0 CMP $0, t0 CSEL EQ, t2, hlp1, hlp1 LDx(z2sqr) LDy(x1in) CALL p256MulInternal<>(SB) // u1 = x1 * z2ˆ2 STy(u1) LDx(z1sqr) LDy(x2in) CALL p256MulInternal<>(SB)...
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jan 29 15:10:35 UTC 2025
    - 635K bytes
    - Viewed (0)
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