'Path to write the genereated register op file and MLIR file.')

flags.DEFINE_bool('gen_register_op', True,
                  'Generate register op cc file or tfr mlir file.')


@Composite(
    'NewMirrorPad',
    inputs=['input_: T', 'paddings: Tpaddings'],
    attrs=['mode: {"REFLECT", "SYMMETRIC"}'],
    derived_attrs=['T: type', 'Tpaddings: {int32, int64} = DT_INT32'],
    outputs=['output: T'])