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Results 1 - 3 of 3 for Meister (0.2 sec)
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src/cmd/asm/internal/asm/testdata/riscv64error.s
MOV $0, 0(SP) // ERROR "constant load must target register" MOV $0, 8(SP) // ERROR "constant load must target register" MOV $1234, 0(SP) // ERROR "constant load must target register" MOV $1234, 8(SP) // ERROR "constant load must target register" MOVB $1, X5 // ERROR "unsupported constant load" MOVH $1, X5 // ERROR "unsupported constant load" MOVW $1, X5 // ERROR "unsupported constant load"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Sun Apr 07 03:32:27 GMT 2024 - 2.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
p.errorf("register list: bad low register in `[%s`", loName) } return } if tok := p.next().ScanToken; tok != '-' { p.errorf("register list: expected '-' after `[%s`, found %s", loName, tok) return } hiName := p.next().String() hi, ok := p.arch.Register[hiName] if !ok { p.errorf("register list: bad high register in `[%s-%s`", loName, hiName) return }
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Feb 21 14:34:57 GMT 2024 - 36.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
// both 1st operand and 3rd operand are (Rs, Rs+1) register pair. // And the register pair must be contiguous. if (a[0].Type != obj.TYPE_REGREG) || (a[2].Type != obj.TYPE_REGREG) { p.errorf("invalid addressing modes for 1st or 3rd operand to %s instruction, must be register pair", op) return } // For ARM64 CASP-like instructions, its 2nd destination operand is register pair(Rt, Rt+1) that can
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Feb 21 14:34:57 GMT 2024 - 25.3K bytes - Viewed (0)