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Results 1 - 10 of 30 for MOVWstore (0.22 sec)

  2. github.com/golang/go

    src/cmd/compile/internal/ssa/_gen/RISCV64.rules 

    (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
(MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWreg  x) mem) => (MOVWstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)

// Replace extend after load with alternate load where possible.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  3. github.com/golang/go

    src/cmd/compile/internal/ssa/_gen/MIPS.rules 

    (Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 =>
		(MOVWstore [4] ptr (MOVWconst [0])
			(MOVWstore [0] ptr (MOVWconst [0]) mem))
(Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 =>
	(MOVWstore [8] ptr (MOVWconst [0])
		(MOVWstore [4] ptr (MOVWconst [0])
			(MOVWstore [0] ptr (MOVWconst [0]) mem)))
(Zero [16] {t} ptr mem) && t.Alignment()%4 == 0 =>
	(MOVWstore [12] ptr (MOVWconst [0])
		(MOVWstore [8] ptr (MOVWconst [0])
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  4. github.com/golang/go

    src/cmd/compile/internal/ssa/_gen/MIPS64.rules 

    (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
(MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)

// if a register move has only 1 use, just use the same register without emitting instruction
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  5. github.com/golang/go

    src/cmd/compile/internal/ssa/_gen/LOONG64.rules 

    (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
(MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)

// if a register move has only 1 use, just use the same register without emitting instruction
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  6. github.com/golang/go

    src/cmd/compile/internal/ssa/_gen/ARM64.rules 

    (Move [4] dst src mem) => (MOVWstore dst (MOVWUload src mem) mem)
(Move [5] dst src mem) =>
	(MOVBstore [4] dst (MOVBUload [4] src mem)
		(MOVWstore dst (MOVWUload src mem) mem))
(Move [6] dst src mem) =>
	(MOVHstore [4] dst (MOVHUload [4] src mem)
		(MOVWstore dst (MOVWUload src mem) mem))
(Move [7] dst src mem) =>
	(MOVWstore [3] dst (MOVWUload [3] src mem)
		(MOVWstore dst (MOVWUload src mem) mem))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  7. github.com/golang/go

    src/cmd/compile/internal/ssa/_gen/S390X.rules 

    (LDGR (LGDR x)) => x
(LGDR (LDGR x)) => x

// Don't extend before storing
(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
(MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWZreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 12 18:09:26 UTC 2023
    - 74.3K bytes
    - Viewed (0)
  8. github.com/golang/go

    src/cmd/compile/internal/ssa/rewriteMIPS.go 

    		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [16] {t} dst src mem)
	// cond: t.Alignment()%4 == 0
	// result: (MOVWstore [12] dst (MOVWload [12] src mem) (MOVWstore [8] dst (MOVWload [8] src mem) (MOVWstore [4] dst (MOVWload [4] src mem) (MOVWstore dst (MOVWload src mem) mem))))
	for {
		if auxIntToInt64(v.AuxInt) != 16 {
			break
		}
		t := auxToType(v.Aux)
		dst := v_0
		src := v_1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 176.6K bytes
    - Viewed (0)
  9. github.com/golang/go

    src/cmd/compile/internal/ssa/_gen/ARM.rules 

    (MOVHstore [off1] {sym} (SUBconst [off2] ptr) val mem) => (MOVHstore [off1-off2] {sym} ptr val mem)
(MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) => (MOVWstore [off1+off2] {sym} ptr val mem)
(MOVWstore [off1] {sym} (SUBconst [off2] ptr) val mem) => (MOVWstore [off1-off2] {sym} ptr val mem)
(MOVFstore [off1] {sym} (ADDconst [off2] ptr) val mem) => (MOVFstore [off1+off2] {sym} ptr val mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  10. github.com/golang/go

    src/cmd/compile/internal/ssa/_gen/AMD64.rules 

    (MOVLstore [off] {sym} ptr (MOVLQSX x) mem) => (MOVLstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWQSX x) mem) => (MOVWstore [off] {sym} ptr x mem)
(MOVBstore [off] {sym} ptr (MOVBQSX x) mem) => (MOVBstore [off] {sym} ptr x mem)
(MOVLstore [off] {sym} ptr (MOVLQZX x) mem) => (MOVLstore [off] {sym} ptr x mem)
(MOVWstore [off] {sym} ptr (MOVWQZX x) mem) => (MOVWstore [off] {sym} ptr x mem)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 93.9K bytes
    - Viewed (0)
  11. github.com/golang/go

    src/cmd/compile/internal/ssa/rewriteLOONG64.go 

    		v1.AddArg3(dst, v2, v3)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [12] {t} dst src mem)
	// cond: t.Alignment()%4 == 0
	// result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVWstore [4] dst (MOVWload [4] src mem) (MOVWstore dst (MOVWload src mem) mem)))
	for {
		if auxIntToInt64(v.AuxInt) != 12 {
			break
		}
		t := auxToType(v.Aux)
		dst := v_0
		src := v_1
		mem := v_2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
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