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Results 1 - 10 of 17 for MOVWUreg (0.15 sec)
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src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules
(MOVWreg x:(MOVBreg _)) => (MOVDreg x) (MOVWreg x:(MOVBUreg _)) => (MOVDreg x) (MOVWreg x:(MOVHreg _)) => (MOVDreg x) (MOVWreg x:(MOVWreg _)) => (MOVDreg x) (MOVWUreg x:(MOVBUreg _)) => (MOVDreg x) (MOVWUreg x:(MOVHUreg _)) => (MOVDreg x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 4.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(MADDW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x)) (MADDW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a) (MADDW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x)) (MADDW a x (MOVDconst [c])) && isPowerOfTwo64(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)])) (MADDW a x (MOVDconst [c])) && isPowerOfTwo64(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64latelower.rules
(SRLI [c] (MOVHUreg x)) && c < 16 => (SRLI [48+c] (SLLI <typ.UInt64> [48] x)) (SRLI [c] (MOVWUreg x)) && c < 32 => (SRLI [32+c] (SLLI <typ.UInt64> [32] x)) (SLLI [c] (MOVBUreg x)) && c <= 56 => (SRLI [56-c] (SLLI <typ.UInt64> [56] x)) (SLLI [c] (MOVHUreg x)) && c <= 48 => (SRLI [48-c] (SLLI <typ.UInt64> [48] x)) (SLLI [c] (MOVWUreg x)) && c <= 32 => (SRLI [32-c] (SLLI <typ.UInt64> [32] x)) // Shift by zero. (SRAI [0] x) => x
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Oct 24 03:45:10 UTC 2022 - 980 bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/RISCV64.rules
(MOVWreg x:(MOVWreg _)) => (MOVDreg x) (MOVBUreg x:(MOVBUreg _)) => (MOVDreg x) (MOVHUreg x:(MOVBUreg _)) => (MOVDreg x) (MOVHUreg x:(MOVHUreg _)) => (MOVDreg x) (MOVWUreg x:(MOVBUreg _)) => (MOVDreg x) (MOVWUreg x:(MOVHUreg _)) => (MOVDreg x) (MOVWUreg x:(MOVWUreg _)) => (MOVDreg x) // Do not extend before store. (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 40.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64latelower.go
return true } // match: (MOVWUreg x:(MOVHUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVHUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpARM64MOVWUreg { break } v.reset(OpARM64MOVDreg) v.AddArg(x) return true }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 19.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(MOVWreg x:(MOVBreg _)) => (MOVVreg x) (MOVWreg x:(MOVBUreg _)) => (MOVVreg x) (MOVWreg x:(MOVHreg _)) => (MOVVreg x) (MOVWreg x:(MOVWreg _)) => (MOVVreg x) (MOVWUreg x:(MOVBUreg _)) => (MOVVreg x) (MOVWUreg x:(MOVHUreg _)) => (MOVVreg x) (MOVWUreg x:(MOVWUreg _)) => (MOVVreg x) // don't extend before store (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
(MOVWreg x:(MOVBreg _)) => (MOVVreg x) (MOVWreg x:(MOVBUreg _)) => (MOVVreg x) (MOVWreg x:(MOVHreg _)) => (MOVVreg x) (MOVWreg x:(MOVWreg _)) => (MOVVreg x) (MOVWUreg x:(MOVBUreg _)) => (MOVVreg x) (MOVWUreg x:(MOVHUreg _)) => (MOVVreg x) (MOVWUreg x:(MOVWUreg _)) => (MOVVreg x) // don't extend before store (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64latelower.go
v.AuxInt = int64ToAuxInt(48 - c) v0 := b.NewValue0(v.Pos, OpRISCV64SLLI, typ.UInt64) v0.AuxInt = int64ToAuxInt(48) v0.AddArg(x) v.AddArg(v0) return true } // match: (SLLI [c] (MOVWUreg x)) // cond: c <= 32 // result: (SRLI [32-c] (SLLI <typ.UInt64> [32] x)) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpRISCV64MOVWUreg { break } x := v_0.Args[0] if !(c <= 32) {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Jan 19 22:42:34 UTC 2023 - 5.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
// cond: int32(c)==0 // result: (MOVWUreg a) for { a := v_0 if v_2.Op != OpARM64MOVDconst { break } c := auxIntToInt64(v_2.AuxInt) if !(int32(c) == 0) { break } v.reset(OpARM64MOVWUreg) v.AddArg(a) return true } // match: (MADDW a x (MOVDconst [c])) // cond: int32(c)==1 // result: (MOVWUreg (ADD <a.Type> a x)) for { a := v_0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteRISCV64.go
break } v.reset(OpRISCV64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg x:(MOVWUreg _)) // result: (MOVDreg x) for { x := v_0 if x.Op != OpRISCV64MOVWUreg { break } v.reset(OpRISCV64MOVDreg) v.AddArg(x) return true } // match: (MOVWUreg <t> x:(MOVWload [off] {sym} ptr mem)) // cond: x.Uses == 1 && clobber(x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 205.1K bytes - Viewed (0)